特殊函數單元的設計中會使用多項式近似目標函數，多項式近似運算的係數會預先計算求得並儲存於查找表中加速硬體計算，然而查找表卻占了整體大部分的面積資源。本論文提出使用分段多項式近似的運算架構，透過不均勻分段(Non-uniform segmentation)設計，減少查找表所需使用面積。我們探討泰勒級數展開(Taylor series expansion method)及最小化極大近似法(Minimax approximation)的近似效果及演算法特性，利用泰勒級數展開較易於分析的特性，透過計算泰勒多項式的餘項設計分段演算法。硬體運算中可經由精準度選擇線，減少多項式運算階數並輸出低精準度的近似運算，設計可變精準度之低功耗運算架構。本篇論文硬體架構使用VerilogHDL語言撰寫，以Design Compiler在TSMC 40nm製程下合成並模擬驗證，並使用Memory Compiler模擬記憶體查找表單元，藉由Primetime程式分析雙重精準度近似單元於不同模式中的功耗。

This paper presents a non-uniform segmentation method for a special function unit based on Taylor series approximation. Compared with the uniform segmentation, our method reduces the sizes of the look-up tables by decreasing the number of segments. By reducing the calculation of polynomial order and partitioning the multipliers, our architecture can output low-precision result with lower power consumption.
The proposed design is synthesized with TSMC 40-nm cell library, and the implementation results based on 2^nd order polynomial approximation show that our method can efficiently reduce the total area by 15% in single-precision.

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