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研究生： 劉彥麟
Liu, Yen-Lin
論文名稱： 支援嵌入式作業系統之模組化32位元RISC-V處理器設計
Design of Modular 32-Bit RISC-V Processor for Embedded Operating System
指導教授： 陳中和
Chen, Chung-Ho
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2023
畢業學年度： 112
語文別： 中文
論文頁數： 73
中文關鍵詞： General Purpose Embedded System 、RISC-V 、Processor 、AXI4
外文關鍵詞： General Purpose Embedded System, RISC-V, Processor, AXI4
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    • 有鑑於近年來Embedded System已被應用於各大領域，如汽車、家電、醫療設備等，因此Embedded System變得越來越多樣化且越來越複雜，開發人員剛開始設計嵌入式產品時，通常對其確切的設計需求不甚了解，若原先的設計要求在產品開發過程中出現變化，開發人員便需要去調整Embedded System的記憶體、功能等硬體相關參數，若開發人員未考慮到可能的變化，則有可能要調整大量的硬體佈局，因此設計具有可擴充性 (Scalability) 之通用型Embedded System變得越來越重要。
    本論文使用Chisel Hardware Description Language開發支援通用型Embedded System之模組化 (Modularization) RISC-V Processor，該模組化RISC-V Processor內部包含：
     RV32IMA_Zifencei_Zicsr Datapath with Machine, Supervisor, User Mode
     Core Local Interrupt Controller
     Sv32 Memory Management Unit
     AXI4 System Bus
     AXI4-Lite Controlled Universal Asynchronous Receiver/Transmitter
    本論文在設計過程中透過參數化 (Parameterization) 與介面標準化 (standardization) 等方式達模組化的目的，由於具有模組化之功能，因此開發人員僅須透過簡單參數修改便可快速產生符合需求之Embedded System，開發人員亦可基於標準化介面研發新的硬體，並將其透過本論文定義之標準化介面與現有硬體系統連接。
    最終本論文透過開發適用模組化RISC-V Processor之韌體，使本論文設計之模組化RISC-V Processor可執行不同的軟體與Embedded Operating System，並透過RISC-V Test、CoreMark、FreeRTOS、OpenSBI等不同的軟體驗證通用型Embedded System之正確性並測試其效能。

    In recent years, embedded systems have been applied in various fields, such as automobiles, household appliances, and medical equipment. As a result, embedded systems have become more and more diversified and complex. When developers first start to design embedded products, they often do not have a clear understanding of their exact design requirements. If the original design requirements change during the product development process, developers need to adjust the hardware-related parameters of the embedded system, such as memory and hardware functionality. If developers do not consider the possible changes or hardcoding some parameters, they may have to adjust a large amount of hardware layout. Therefore, it is becoming increasingly important to design a general-purpose embedded system with scalability.
    In this thesis, we present the design and implementation of a general-purpose embedded system based on the RISC-V instruction set architecture. We use Chisel Hardware Description Language (HDL) to develop a modular RISC-V processor, and we use the modular RISC-V processor as single-chip microcomputer of the general-purpose embedded system. Developers can simply get processor with different performance by changing parameters of the modular RISC-V processor. Developers can also get processor with new functionality by adding customized hardware based on standardized interfaces.
    In the final experiment, we verify the correctness and performance of the general-purpose embedded system with different software, such as RISC-V Test, CoreMark, FreeRTOS, and OpenSBI.

    摘要 I 誌謝 VIII 目錄 IX 圖目錄 XII 表目錄 XV 第1章 緒論 1 1.1 論文動機 1 1.2 論文貢獻 2 1.3 論文架構 2 第2章 背景知識 3 2.1 Chisel Hardware Description Language 3 2.2 RISC-V Instruction Set Architecture 4 2.2.1 Introduction of RISC-V Instruction Set Architecture 4 2.2.2 RISC-V Unprivileged Instruction Set 5 2.2.3 RISC-V Privileged Instruction Set 13 2.2.4 Sv32: Page-Based 32-bit Virtual Memory Systems 17 2.2.5 Core Local Interrupt 21 2.3 AXI4 Protocol 21 2.3.1 Introduction of AXI4 Protocol 22 2.3.2 AXI4 Interface 22 2.3.3 AXI4 Channel 23 2.3.4 AXI4 Transaction 24 2.4 AXI4-Lite Controlled UART 27 2.4.1 Introduction of UART 27 2.4.2 Hardware of AXI4-Lite Controlled UART 28 2.4.3 Software of AXI4-Lite Controlled UART 30 2.5 Embedded Operating System 31 2.5.1 Introduction of Embedded Operating System 31 2.5.2 FreeRTOS 31 2.5.3 Embedded Linux 32 第3章 問題分析與設計方法 35 3.1 Design of CASLab RISC-V Processor 35 3.2 Design of CASLab RISC-V Core 38 3.2.1 RV32IMA Datapath 40 3.2.2 Configurable Cache 43 3.2.3 Sv32 Memory Management Unit 49 3.2.4 Access Interface 53 3.3 Design of AXI4 System Bus 56 3.3.1 AXI4 Master 56 3.3.2 AXI4 Slave 56 3.3.3 AXI4 Bridge 57 3.4 Software for CASLab RISC-V Processor 59 3.4.1 Device Driver for AXI4-Lite Controlled UART 59 3.4.2 Device Tree for CASLab RISC-V Processor 60 第4章 實驗結果與效能分析 61 4.1 實驗平台環境介紹 61 4.2 實驗結果與分析 63 4.2.1 Unit Testing 63 4.2.2 System Testing 64 4.2.3 CoreMark 66 4.2.4 FreeRTOS 68 4.2.5 OpenSBI 70 第5章 結論與未來展望 72 5.1 結論 72 5.2 未來展望 72 參考文獻 73

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