| 研究生: |
馬平 Ma, Ping |
|---|---|
| 論文名稱: |
非線性訊號處理用於降低射頻不完美之FPGA與GPU開發 FPGA and GPU Design Explorations of Nonlinear Signal Processing for RF Impairment Mitigation |
| 指導教授: |
郭致宏
Kuo, Chih-Hung |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2013 |
| 畢業學年度: | 101 |
| 語文別: | 英文 |
| 論文頁數: | 63 |
| 中文關鍵詞: | 正交分頻多工系統 、載波頻率位移 、IQ不平衡 、高階合成 、運算統一計算架構 |
| 外文關鍵詞: | Orthogonal frequency division multiplexing (OFDM), Carrier Frequency Offset, IQ Imbalance, High-level synthesis (HLS), Compute Unified Device Architecture (CUDA) |
| 相關次數: | 點閱:127 下載:2 |
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本論文提出可接受大範圍載波頻率偏移之IQ不平衡與載波頻率偏移共同補償演算法完整數學模型。此大範圍載波頻率偏移分為三個子頻帶,並依據其載波頻率的大小分別有低頻區最小平方法、中頻區最小平方法與高頻區短序文最小平方法。透過短序文的使用,所估測的載波頻率範圍可擴大四倍,並且依然維持高估測準確度。本論文使用高階合成 (High-level synthesis, HLS)將演算法實現到FPGA。此演算法也將使用圖像處理器 (Graphic Processing Unit, GPU)中運算統一計算架構(Compute Unified Device Architecture)加速演算法之運算速度,將演算法中可平行運算之部分以具有高速平行運算能力的顯示卡代理達到加速的效果。結果顯示我們所提出基於最小平方法的演算法在大範圍的載波頻率偏移下仍提供高度的準確性,使用高階合成可加速演算法實現到FPGA速度,演算法可快速地模擬得知所需硬體資源變動與效能變化。GPU的使用了加速演算法的運算速度。
In this paper, we propose a complete mathematical model for a wide-range-CFO joint CFO and IQ imbalance compensation algorithm. The wide range of CFO is divided into three parts. According to the value of CFO, we have the Low-CFO Least-Square algorithm, the Least-Square algorithm, and the Short Preamble High-CFO Least-Square algorithm. By utilizing short preamble, the estimable range of CFO can be enlarged four times than only using short preamble and providing accurate estimate. Considering the hardware behavior when simulating the algorithm in C language, we apply High-Level Synthesis (HLS) to implement the algorithm on FPGA. We also apply Compute Unified Device Architecture (CUDA), one of the Graphic Processing Units (GPU), to accelerate the computing speed. Results show that our algorithm provides highly accurate estimate under very large range of CFO. HLS provides fast simulation in design phase.
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