由於NAND型快閃記憶體高密度、高通量及低功率的特性，快閃記憶體已被廣泛應用在儲存裝置。然而，隨著快閃記憶體製程的持續微縮和多階層儲存單元技術之發展，如何確保資料的可靠度成為重要的探討議題。本篇論文主要是針對預防及修正錯誤的機制研究。
本論文針對兩個主要的研究主題：快閃記憶體訊號處理及錯誤更正碼。首先針對快閃記憶體的訊號處理，我們提出評估錯誤數量之機制來減少錯誤更正碼解碼失敗的次數。此外，我們延用鄰接記憶單元輔助修正錯誤機制之架構，修正由於寫入操作所造成的記憶單元間干擾之誤判錯誤，並且獲取特定記憶單元的軟式資訊。
針對錯誤更正碼應用之探討，本論文提出連結張量乘積碼及軟式決策BCH解碼器。為了克服硬式決策BCH解碼器的修正能力極限，可採用Chase類型演算法利用最不可靠位元之集合來增進錯誤修正能力。然而，由於快閃記憶體本身的限制，硬式決策讀取的輸出造成獲取軟式資訊的困難。雖然多次感測技術的應用能取得軟式資訊，但是多次的感測和資料輸出操作也造成大量的延遲和能量消耗。因此，我們提出利用張量乘積碼當作內碼，從快閃記憶體之硬式決策輸出萃取最不可靠位元的集合，提供給作為外碼之軟式決策錯誤更正碼。
在不同層面評估下，本論文所提出的(8624, 8192)連結張量乘積碼及軟式決策BCH解碼器可以達到於每一千位元組資料中修正40個錯誤位元的能力。若與2Y奈米MLC快閃記憶體公稱壽命比較，有大約5.67倍的壽命提升，若和使用全域優化讀取參考電壓判決資料的記憶體之壽命比較，則有1.17倍的壽命幅度成長，其代價為大約2.81倍的(8528, 8192, 24) BCH解碼器之硬體面積。所提出的張量乘積碼與多次感測技術比較則可省下至少237.9 微秒至多672微秒的感測延遲，並且減少至少1.75 nJ/byte至多5.06 nJ/byte能量消耗。

NAND flash memory has been widely used for data storage due to its high density, high throughput, and low power. However, data reliability becomes a serious issue with the continued scaling of NAND flash and multi-level cell technology. As a result, the mechanisms to prevent or correct errors are discussed in this dissertation.
We investigated two major research topics: flash memory signal processing and error correction codes. For the first topic, we proposed an approach that can be applied to estimate error numbers to reduce the decoding failure of error correction codes. Furthermore, we adopted the architecture of neighbor-assisted correction mechanism to correct the misread errors due to cell-to-cell program interference and obtain the soft information for specific memory cells.
For the second topic, a concatenated tensor product code and soft-decision BCH decoder is proposed. To overcome the limit of hard-decision BCH decoder, the Chase-typed BCH decoder is employed to enhance the error correction capability with the set of the least reliable bits. However, the fact that NAND flash memories only provide hard decision output causes the problem of obtaining soft information. The multiple sensing scheme was proposed to solve this problem, but it increase the significantly latency and energy consumption of sensing and data output operations. Therefore, we proposed to use the tensor product code as the inner code to extract the least reliable bits from hard decision outputs of NAND flash memory for the soft-decision outer code.
From different aspects of evaluation, the proposed (8624, 8192) concatenated tensor product code and soft-decision BCH decoder can correct 40 error bits per 1k-Byte data, reach about 5.67 times lifetime of 2Y-nm MLC flash memory compared with the nominal lifetime, and increase 1.17 times lifetime compared with the memory using overall read reference voltage to read out data. The overhead is around 2.81 times the area of (8528,8192,24) BCH decoder. The proposed tensor product codes can save the latency by at least 237.9 μs up to 672 μs compared with the multiple sensing scheme, and reduce at least 1.75 nJ/byte up to 5.06 nJ/byte about energy consumption as well.

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