| 研究生: |
柯柏豪 Ko, Po-Hao |
|---|---|
| 論文名稱: |
NAND型快閃記憶體其周邊電路元件之特性與可靠度研究 Device characteristics and reliability related to NAND flash peripheral circuit |
| 指導教授: |
陳志方
Chen, Jone-Fang |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 微電子工程研究所 Institute of Microelectronics Engineering |
| 論文出版年: | 2021 |
| 畢業學年度: | 109 |
| 語文別: | 英文 |
| 論文頁數: | 58 |
| 中文關鍵詞: | N型空乏式高壓金氧半場效電晶體 、崩潰電壓 、熱載子影響的可靠度與生命週期 、電腦輔助設計模擬 |
| 外文關鍵詞: | N-type depletion-mode high-voltage metal-oxide-semiconductor field-effect transistors, off-state breakdown voltage, hot-carrier reliability and lifetime, TCAD simulation |
| 相關次數: | 點閱:216 下載:0 |
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NAND flash擁有高存取速度、低單位成本、低功率消耗、與高儲存密度的優點,適合使用在大量儲存裝置,而現今廣泛應用在行動電子產品當中。而在本篇研究論文中,主要的研究目的在於NAND Flash的周邊電路的相關元件的元件特性與可靠度的研究。而在本篇研究論文中,使用的是在NAND Flash的周邊電路內部的高壓元件,N型空乏式高壓金氧半場效電晶體。由於高壓元件長期在高電壓的環境下操作,崩潰電壓與熱載子影響的可靠度與生命週期為相當重要的元件參數。由於探討這種類型的元件的文獻並不多,所以我們以此作為此次研究的目標。
在本論文中,我們針對不同布局參數(L&Lgd)與特殊結構(漸變接面)的N型空乏式高壓金氧半場效電晶體的特性以及熱載子影響的可靠度進行探討並進一步了解物理機制,重要的布局參數L為閘極長度,Lgd為飄移區長度。
在基本介紹過後,接著將會介紹量測元件時的設定方法與量測結果,之後再藉由電腦輔助設計模擬來觀察元件的內部變化,並推測物理機制。我們發現增加L和增加Lgd和使用漸變接面的結構會因為電場分布的改變而改善崩潰電壓、也會降低基板電流(Isub)並降低退化而使元件壽命增加。
NAND flash memory has the advantages of high access speed, low unit cost, low power consumption, and high storage density. It is also suitable for use in a mess storage devices, and has been widely applied to 3C mobile products. In this paper, the main research purpose is to study the device characteristics and reliability related to NAND flash peripheral circuit. The research in this paper uses high-voltage device which used in the peripheral circuits of NAND Flash, N-type depletion-mode high-voltage metal-oxide-semiconductor field-effect transistors. Because high-voltage device usually operated under high-voltage, the off-state breakdown voltage and hot-carrier reliability and lifetime are very important device parameters. Because there are not many literatures investigate this type of device, so we take this as the objective of this research.
In this paper, we discuss the characteristics and hot-carrier reliability of N-type depletion-mode high-voltage metal-oxide-semiconductor field-effect transistors with different layout parameters (L&Lgd) and special structures (gradual junction) and further understand the physics mechanism inside the device. The important layout parameter L is the gate length, and Lgd is the length of drift region. After the fundamental introduction, the measurement setup and methodology when measuring the device, and then we use Technology Computer Aided Design(TCAD) to simulation the internal variation, and consider the physical mechanism. We found that increasing L and increasing Lgd and using the structure of the gradual junction can improve the breakdown voltage, decrease the substrate current (Isub) and decrease the degradation to increase the lifetime of the device.
[1] Bianchi, R. A., et al. "High voltage devices integration into advanced CMOS technologies." 2008 IEEE International Electron Devices Meeting. IEEE, 2008.
[2] Parpia, Zahir, C. Andre T. Salama, and Robert A. Hadaway. "A CMOS-compatible high-voltage IC process." IEEE Transactions on Electron Devices 35.10 (1988): 1687-1694.
[3] Meyer, W. G., et al. "Integrable high voltage CMOS: Devices, process application." 1985 International Electron Devices Meeting. IEEE, 1985.
[4] Terashima, Tomohide, Fumitoshi Yamamoto, and Kenichi Hatasako. "Multi-voltage device integration technique for 0.5/spl mu/m BiCMOS and DMOS process." 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No. 00CH37094). IEEE, 2000.
[5] Manzini, S., A. Gallerano, and C. Contiero. "Hot-electron injection and trapping in the gate oxide of submicron DMOS transistors." Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No. 98CH36212). IEEE, 1998.
[6] Chen, Shiang-Yu, et al. "Anomalous hot-carrier-induced increase in saturation-region drain current in n-type lateral diffused metal–oxide–semiconductor transistors." IEEE transactions on electron devices 55.5 (2008): 1137-1142.
[7] Chen, Jone F., et al. "Drift region doping effects on characteristics and reliability of high-voltage n-type metal–oxide–semiconductor transistors." Japanese Journal of Applied Physics 55.1S (2015): 01AD03.
[8] Brisbin, Douglas, Andy Strachan, and Prasad Chaparala. "Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications." 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No. 02CH37320). IEEE, 2002.
[9] Shrivastava, Mayank, et al. "Part I: Mixed-signal performance of various high-voltage drain-extended MOS devices." IEEE transactions on electron devices 57.2 (2009): 448-457.
[10] Brisbin, D., P. Lindorfer, and P. Chaparala. "Substrate current independent hot carrier degradation in NLDMOS devices." 2006 IEEE International Reliability Physics Symposium Proceedings. IEEE, 2006.
[11] Chen, Jone F., et al. "An investigation on anomalous hot-carrier-induced on-resistance reduction in n-type LDMOS transistors." IEEE Transactions on Device and Materials Reliability 9.3 (2009): 459-464.
[12] Chen, Ja-Hao, Shyh-Chyi Wong, and Yeong-Her Wang. "An analytic three-terminal band-to-band tunneling model on GIDL in MOSFET." IEEE Transactions on Electron Devices 48.7 (2001): 1400-1405.
[13] Choi, Yang-Kyu, et al. "Investigation of gate-induced drain leakage (GIDL) current in thin body devices: single-gate ultra-thin body, symmetrical double-gate, and asymmetrical double-gate MOSFETs." Japanese journal of applied physics 42.4S (2003): 2073.
[14] Semenov, Oleg, Andrzej Pradzynski, and Manoj Sachdev. "Impact of gate induced drain leakage on overall leakage of submicrometer CMOS VLSI circuits." IEEE Transactions on semiconductor manufacturing 15.1 (2002): 9-18.
[15] Chan, T. Y., et al. "The impact of gate-induced drain leakage current on MOSFET scaling." 1987 International Electron Devices Meeting. IEEE, 1987.
[16] Choi, Yang-Kyu, et al. "Investigation of gate-induced drain leakage (GIDL) current in thin body devices: single-gate ultra-thin body, symmetrical double-gate, and asymmetrical double-gate MOSFETs." Japanese journal of applied physics 42.4S (2003): 2073.
[17] Hu, Chenming. Modern semiconductor devices for integrated circuits. Vol. 2. Upper Saddle River, New Jersey: Prentice Hall, 2010.
[18] Wolf, Stanley. "Silicon Processing for the VLSI era, Vol. 3: The submicron MOSFET." (1994).
[19] Hu, Chenming, et al. "Hot-electron-induced MOSFET degradation-model, monitor, and improvement." IEEE Journal of Solid-State Circuits 20.1 (1985): 295-305.
[20] Silvaco, Int. "ATLAS user’s manual." Santa Clara, CA, Ver 5 (2011).
[21] Shvetsov-Shilovskiy, I. I., et al. "Measurement system for test memory cells based on keysight B1500A semiconductor device analyzer running LabVIEW software." 2017 International Siberian Conference on Control and Communications (SIBCON). IEEE, 2017.
[22] Reggiani, Susanna, et al. "Physics-based analytical model for HCS degradation in STI-LDMOS transistors." IEEE transactions on electron devices 58.9 (2011): 3072-3080.
[23] Colak, Sel. "Effects of drift region parameters on the static properties of power LDMOST." IEEE transactions on electron devices 28.12 (1981): 1455-1466.
[24] Chan, T. Y., P. K. Ko, and C. Hu. "A simple method to characterize substrate current in MOSFET's." IEEE Electron Device Letters 5.12 (1984): 505-507.
[25] Quader, Khandker N., et al. "A bidirectional NMOSFET current reduction model for simulation of hot-carrier-induced circuit degradation." IEEE Transactions on Electron Devices 40.12 (1993): 2245-2254.
[26] Varghese, D., et al. "Simulation and modeling of hot carrier degradation of cascoded NMOS transistors for power management applications." 2012 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2012.
[27] Moens, Peter, and Guido Groeseneken. "Hot-carrier degradation phenomena in lateral and vertical DMOS transistors." IEEE Transactions on Electron Devices 51.4 (2004): 623-628.
[28] Moens, P., et al. "A comprehensive model for hot carrier degradation in LDMOS transistors." 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual. IEEE, 2007.
[29] Moens, Peter, and Geert Van den Bosch. "Characterization of total safe operating area of lateral DMOS transistors." IEEE transactions on device and materials reliability 6.3 (2006): 349-357.
[30] Wang, Lei, et al. "Physical description of quasi-saturation and impact-ionization effects in high-voltage drain-extended MOSFETs." IEEE transactions on electron devices 56.3 (2009): 492-498.
[31] Ng, K. H., et al. "A comparison of interface trap generation by Fowler-Nordheim electron injection and hot-hole injection using the DCIV method." Proceedings of the 1999 7th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No. 99TH8394). IEEE, 1999.
[32] Hamada, Akemi, et al. "A new aspect of mechanical stress effects in scaled MOS devices." IEEE transactions on electron devices 38.4 (1991): 895-900.
[33] Chen, Jone F., et al. "Analysis of high-voltage metal–oxide–semiconductor transistors with gradual junction in the drift region." Japanese Journal of Applied Physics 55.8S2 (2016): 08PD04.
[34] Yen-Lin Tsai, et al. “Investigation of characteristics and hot-carrier reliability of high-voltage MOS transistors with various doping concentrations in the drift region” Semicond. Sci. Technol.33 (2018) 125019 (7pp)
[35] Jone F. Chen, et al. “Characteristics and reliability of metal–oxide–semiconductor transistors with various depths of plasma-induced Si recess structure” Japanese Journal of pplied Physics 57, 04FD01 (2018)
[36] Chin-Rung Yan, et al. “Characteristics of Lateral Diffused Metal–Oxide–Semiconductor Transistors with Lightly Doped Drain Implantation through Gradual Screen Oxide” Japanese Journal of Applied Physics 52 (2013) 04CC07
[37] Jone F. Chen, et al. “Analysis of GIDL-InducedOFF-State Breakdown in High-Voltage Depletion-Mode nMOSFETs” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 6, JUNE 2011