由於電子電路製程技術的進步，讓單一晶片擁有更多不同的功能。單晶片的系統複雜化，使驗證單晶片系統的時間逐漸增加，更因此拖延產品的上市時間(Time to Market)。如何在系統設計初期即能夠驗證其功能性已成為重要的議題。
為了達到這個目標，本論文利用嵌入式虛擬平台的概念，提供一個驗證系統功能性的環境。相較於低抽象層級的RTL模型，以高抽象層級的TLM來建立系統將會更加快速且有效率。本論文利用SystemC程式語言建立以TLM為基礎的嵌入式虛擬平台，虛擬平台的架構規劃以真實開發版為基礎，建立具有良好的速度、靈活性與功能性的嵌入式虛擬平台。並依據這些基礎以改進虛擬平台的架構，如：提出模擬硬體中斷的機制，使SystemC所模擬的硬體能夠與QEMU使用者模式的CPU進行溝通；並在此CPU中實現大量傳輸資料的模式，以降低整體系統的模擬時間；估計QEMU所模擬之CPU操作頻率，令使用者在系統設計初期即能夠獲知軟體的運算複雜度，最後提出整合QEMU使用者模式之模擬雙核心CPU的方法，建立雙核心的虛擬平台，以提供雙核心系統設計初期時，能夠有快速驗證其功能性的虛擬平台。

With the advance of IC design technology, a single chip can have various functionalities. However, as the system complexity grows, the time for testing and approving a system on chip (SoC) also raises. How to evaluate the performance of a system in the early stages of design becomes an important issue in recent years.
To solve this problem, a virtual platform based verification method can help designers to reduce verification time during the development of a complex System on Chip (SoC) system. The effective way to speed up HW/SW co-simulation is to raise the abstraction levels from RTL to TLM. In this thesis, we use a SystemC based TLM and QEMU to implement a virtual platform that is built with speed, portable, and flexibility. According to these features, we increase the functionalities of the virtual platform with QEMU, including: hardware interrupt, burst mode transfer data, estimate the complexity of software and establish a dual core virtual platform.

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