本論文採用Top-down混層式設計驗證流程實現一個針對可攜式產品應用之數位控制降壓型電源轉換晶片，使用製程為TSMC 0.18-μm 1P6M CMOS製程，除外掛電感、電容外，其餘電路都整合於晶片中。
設計流程一開始無論類比或數位電路都先用Verilog-AMS建立行為模型，並過頂層驗證訂出子電路之規格，類比電路以此選擇適當電路架構進行電晶體層級的設計；數位電路著手撰寫硬體描述語言(Verilog)，再進行數位電路合成得到電晶體層級之電路。完成全系統電晶體層級設計後，開始進行佈局設計並整合於同一晶片中，驗證系統正確且符合規格後即可進行下線動作完成晶片設計。
使用行為模型除了能減少初期混合訊號電路頂層驗證所需模擬時間，也可在滿足系統效能條件下獲得最低限度子電路之規格，避免Over-design。搭配混層式驗證逐步將完成設計之電晶體電路代換原本的行為模型區塊，並且能在代換過程立刻知道電晶體電路之功能是否符合預期，能降低除錯難度加速晶片設計時間。
在降壓型轉換器晶片中，功率開關之面積及功耗皆佔大部分，因此設計功率開關之尺寸為關鍵所在。本論文以全負載範圍滿足效率規格為前提，考慮與電晶體尺寸相關之損耗作分析得最佳電晶體設計尺寸，除了能減少晶片面積也能滿足低功耗之要求。

In this thesis, we realized a mixed-level design methodology to design a digitally-controlled buck converter for portable devices application. The chip was manufactured by TSMC 0.18-μm CMOS process technology. In addition to the external inductance and capacitance, the rest of the circuit were integrated in the chip.
At the beginning of the design, we build the behavioral models for both analog and digital circuits. Then, we can set specifications of the sub-circuit through the top-level verification. Based on specifications, analog circuits select appropriate circuit architectures for transistor-level circuit design, and digital circuits start to write a hardware description language (Verilog), and futher synthesis to transistor-level circuit. After complete the whole system transistor-level design, we integrate all the sub-circuits in the same chip. Finally, we verify the results of the system and check whether the performance meet the specifications.
Using the behavioral model can not only reduce lots of simulation time in the beginning of top-level verification, but also obtain the adequate sub-circuit specifications which can avoid over-design. By replacing the transistor-level circuits with behavioral-level circuits gradually, we can immediately know whether the function of the transistor circuit is work or not, which reduce the time to debug and accelerate the design time.

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