| 研究生: |
謝毅賢 Shie, Yi-Shian |
|---|---|
| 論文名稱: |
高效能視訊編碼標準之環內濾波器在圖形處理器上平行實現 Parallel Implementation for In-Loop Filter of HEVC on GPU |
| 指導教授: |
郭致宏
Kuo, Chih-Hung |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2014 |
| 畢業學年度: | 102 |
| 語文別: | 中文 |
| 論文頁數: | 109 |
| 中文關鍵詞: | 高效能視訊編碼 、環內濾波器 、平行處理 、圖行處理器 |
| 外文關鍵詞: | HEVC, In-Loop Filter, Parallel Processing, GPU |
| 相關次數: | 點閱:87 下載:1 |
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本論文為了減少環內濾波器的執行時間提出一個運行在圖形處理器與中央處理器上的平行程式架構。環內濾波器包含去方塊濾波器與樣本自適應性補償。在去方塊濾波器,我們使用邊緣層級的資料並行性過濾區塊邊緣,且跳過四分樹區塊分割演算法與Z掃描處理順序。在樣本自適應性補償,根據處理流程在每一步的功能將演算法分割成資料統計單元、參數決定單元、與樣本補償單元。對於資料統計單元,我們採用原子加法與平行縮減克服記憶體平行累加的問題。在參數決定單元為了實現位元率平行估算,我們採用資訊估算函數取代上下文自適應性二元算術編碼。最後樣本補償單元基於樣本之間的資料並行性平行補償每一個樣本。實驗結果顯示所提出的平行程式架構在去方塊濾波器可達到5.0倍的增速,樣本自適應性補償可達到10.5倍的增速。
This thesis proposes a parallel program architecture which is running on GPU and CPU to reduce execution time for in-loop filter of HEVC. The in-loop filter includes de-blocking filter and sample adaptive offset. In the de-blocking filter, we use edge-level data parallelism to filter block edges in parallel that skips quadtree decomposition algorithm and z-scan order process. For the sample adaptive offset, we divide sample adaptive offset into statistics calculation, parameters decision, and sample compensation. In the statistics calculation, we use atomic addition and parallel reduction methods to overcome the issue about parallel accumulate for memory. Moreover, we employ a function of information estimation to estimate bitrate instead of context-adaptive binary arithmetic coding for the parameters decision. Finally, the sample compensation compensates samples parallelly based on sample-level data parallelism. Experimental results show that the proposed parallel program architecture achieve 5.0 speedup for de-blocking filter and 10.5 speedup for sample adaptive offset.
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