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研究生: 鄭大偉
Zheng, Da-Wei
論文名稱: 具有抑制中性點電壓擾動現象之三相T型多階變流器
Mitigation of Voltage Fluctuation on the Neutral Point of a Three-phase T-type Multilevel Inverter
指導教授: 張簡樂仁
Chang-Chien, Le-Ren
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2020
畢業學年度: 108
語文別: 中文
論文頁數: 85
中文關鍵詞: 多階變流器中性點箝位式T型變流器電容電壓擾動零序成分注入法
外文關鍵詞: Multilevel Inverter, Neutral-Point-Clamped, T-type Inverter, Zero-Sequence Component Injection
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  • 近年來的製造業以及再生能源等對於中、大功率的電力裝置有著龐大需求,電力變流器在其中扮演重要的角色。然而提昇功率等級之後,傳統二階變流器必須使用規格更高的功率開關,切換損失、電磁干擾等電氣問題變得更加嚴重,而多階變流器克服上述電氣限制,且擁有良好的輸出品質,逐漸受到廣泛應用。不過中性點箝位式以及T型多階變流器皆含有中性點電壓擾動的問題,從而影響變流器的輸出品質。
    本論文旨在實現基於正弦脈衝寬度調變(SPWM),以零序成分注入法抑制中性點電壓擾動的改善方法,並應用至三相三階T型變流器。本文將首先介紹變流器架構與調變技術,接著利用數學模型說明直流側電容電壓擾動的成因,以及軟硬體兩種層面的改善理念,最後透過模擬軟體與實作驗證改善方法的可行性且觀測實際效果。

    Recently, the manufacturing industry and renewable energy require numerous medium and high-power devices, power inverters play a significant role among those applications. However, two-level inverters must use the power switches with higher voltage rating for the increase of capacity rating. It would induce extra switching loss and suffer from electromagnetic interference. Alternatively, multilevel inverters can overcome the aforementioned restrictions and achieve better output performance. Nevertheless, both neutral-point-clamped (NPC) and T-type multilevel inverters have the voltage fluctuation issue on their neutral-points, which could impact the output voltage quality. This research employs a method to mitigate voltage fluctuation on the neutral-point using zero-sequence component injection to the sinusoidal pulse-width modulation. Mathematical analysis of voltage fluctuation on the neutral-point has been illustrated, followed by the improvement using the software and hardware approaches. The effectiveness of the pro-posed method is validated through both simulation and experiment results.

    摘要 I Abstract II SUMMARY III 誌謝 XIV 目錄 XV 表目錄 XVIII 圖目錄 XIX 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機與目的 2 1.3 文獻回顧 3 1.4 論文章節概要 6 第二章 多階變流器 8 2.1 前言 8 2.2 二階變流器 9 2.3 多階變流器 10 2.3.1 多階變流器的特點 12 2.3.2 拓樸架構 13 2.4 中性點箝位式多階變流器 15 2.5 T型多階變流器 19 2.6 架構比較 21 第三章 變流器調變技術 23 3.1 前言 23 3.2 二階正弦脈衝寬度調變 23 3.2.1 雙極性調變 25 3.2.2 單極性調變 26 3.3 空間向量 28 3.3.1 電壓空間向量概念 29 3.3.2 空間向量調變 30 3.4 多階變流器調變技術 34 3.4.1 多階正弦脈衝寬度調變 34 3.4.2 多階空間向量 36 3.5 三次諧波注入法 38 第四章 中性點電壓擾動 42 4.1 前言 42 4.2 中性點數學模型 42 4.3 硬體改善 47 4.4 軟體改善 52 第五章 模擬與實測結果 57 5.1 前言 57 5.2 模擬架構與結果 57 5.3 實驗架構 62 5.3.1 電壓感測電路 63 5.3.2 電流感測電路 64 5.3.3 功率開關與驅動電路 65 5.4 實作驗證 67 第六章 結論與未來展望 79 6.1 結論 79 6.2 未來展望 80 參考文獻 81

    [1] A. Nabae, I. Takahashi and H. Akagi, "A New Neutral-Point-Clamped PWM Inverter," in IEEE Transactions on Industry Applications, vol. IA-17, no. 5, pp. 518-523, Sept. 1981, doi: 10.1109/TIA.1981.4503992.
    [2] J. Rodriguez et al., "Multilevel Converters: An Enabling Technology for High-Power Applications," in Proceedings of the IEEE, vol. 97, no. 11, pp. 1786-1817, Nov. 2009, doi: 10.1109/JPROC.2009.2030235.
    [3] Omar, R., Rasheed, M., Al-janad, A., & Sulaiman, M. (2014). Harmonic Reduction for Diode Clamped and Cascaded H-Bright, Five to Nine Levels of Multilevel Inverters Application.
    [4] 江彥銘。「三相多階中點箝位變流器之研製」。碩士論文,國立高雄應用科技大學電機工程系博碩士班,2014。
    [5] 林佳勳。「三相中性點箝位多階馬達驅動器之研製」。碩士論文,國立高雄應用科技大學電機工程系博碩士班,2015。
    [6] Muhammad H. Rashid. 1993. Power electronics (2nd ed.): circuits, de-vices, and applications. Prentice-Hall, Inc., USA.
    [7] 徐福三。「多階直流-交流功率轉換器架構與脈波寬度調變技術之發展」。博士論文,國立臺北科技大學機電科技研究所,2005。
    [8] Chudasama, Mitrajsinh J., P. N. Tekwani, Siddharthsingh K. Chauhan and Vinod Patel. “Simulation , Design , and Analysis of Three-Level Shunt Active Harmonic Filter using T-Type NPC Topology.” (2017).
    [9] K. Lee, H. Shin and J. Choi, "Comparative analysis of power losses for 3-Level NPC and T-type inverter modules," 2015 IEEE International Telecommunications Energy Conference (INTELEC), Osaka, 2015, pp. 1-6, doi: 10.1109/INTLEC.2015.7572357.
    [10] M. Schweizer, I. Lizama, T. Friedli and J. W. Kolar, "Comparison of the chip area usage of 2-level and 3-level voltage source converter topolo-gies," IECON 2010 - 36th Annual Conference on IEEE Industrial Electronics Society, Glendale, AZ, 2010, pp. 391-396, doi: 10.1109/IECON.2010.5674994.
    [11] K. A. Tehrani, I. Rasoanarivo, H. Andriatsioharana and F. M. Sargos, "A new multilevel inverter model NP without clamping diodes," 2008 34th Annual Conference of IEEE Industrial Electronics, Orlando, FL, 2008, pp. 466-472, doi: 10.1109/IECON.2008.4757998.
    [12] Salem, A., Abido, M.A. T-Type Multilevel Converter Topologies: A Comprehensive Review. Arab J Sci Eng 44, 1713–1735 (2019). https://doi.org/10.1007/s13369-018-3506-6
    [13] M. Schweizer and J. W. Kolar, "High efficiency drive system with 3-level T-type inverter," Proceedings of the 2011 14th European Con-ference on Power Electronics and Applications, Birmingham, 2011, pp. 1-10.
    [14] M. Schweizer and J. W. Kolar, "Design and Implementation of a Highly Efficient Three-Level T-Type Converter for Low-Voltage Applications," in IEEE Transactions on Power Electronics, vol. 28, no. 2, pp. 899-907, Feb. 2013, doi: 10.1109/TPEL.2012.2203151.
    [15] H. Kurumatani and S. Katsura, "GaN-HEMT-based three level T-type NPC inverter using reverse-conducting mode in rectifying," 2017 IEEE 26th International Symposium on Industrial Electronics (ISIE), Edin-burgh, 2017, pp. 1941-1946, doi: 10.1109/ISIE.2017.8001548.
    [16] Chung-Ming Young and Ting-Ruei Fan, "Two-stage interleaved three-level DC/AC converter with neutral point voltage balanc-ing," 2017 IEEE 3rd International Future Energy Electronics Confer-ence and ECCE Asia (IFEEC 2017 - ECCE Asia), Kaohsiung, 2017, pp. 1430-1434, doi: 10.1109/IFEEC.2017.7992254.
    [17] Qian, P., Ma, X., Liu, G. et al. Reducing neutral-point voltage fluctua-tion in NPC three-level active power filters. Electr Eng 100, 721–732 (2018). https://doi.org/10.1007/s00202-017-0538-y
    [18] S. Busquets-Monge, J. Bordonau, D. Boroyevich and S. Somavilla, "The nearest three virtual space vector PWM - a modulation for the comprehensive neutral-point balancing in the three-level NPC inverter," in IEEE Power Electronics Letters, vol. 2, no. 1, pp. 11-15, March 2004, doi: 10.1109/LPEL.2004.828445.
    [19] Y. Zhang, J. Li, X. Li, Y. Cao, M. Sumner and C. Xia, "A Method for the Suppression of Fluctuations in the Neutral-Point Potential of a Three-Level NPC Inverter With a Capacitor-Voltage Loop," in IEEE Transactions on Power Electronics, vol. 32, no. 1, pp. 825-836, Jan. 2017, doi: 10.1109/TPEL.2016.2536176.
    [20] S. Calligaro, F. Pasut, R. Petrella and A. Pevere, "Modulation techniques for three-phase three-level NPC inverters: A review and a novel solution for switching losses reduction and optimal neutral-point balancing in photovoltaic applications," 2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), Long Beach, CA, 2013, pp. 2997-3004, doi: 10.1109/APEC.2013.6520725.
    [21] X. Zhou and S. Lu, "A simple zero-sequence voltage injection method to balance the neutral-point potential for three-level NPC inverters," 2018 IEEE Applied Power Electronics Conference and Exposition (APEC), San Antonio, TX, 2018, pp. 2471-2475, doi: 10.1109/APEC.2018.8341364.
    [22] J. Lee and K. Lee, "Time-Offset Injection Method for Neutral-Point AC Ripple Voltage Reduction in a Three-Level Inverter," in IEEE Transac-tions on Power Electronics, vol. 31, no. 3, pp. 1931-1941, March 2016, doi: 10.1109/TPEL.2015.2439689.
    [23] Qiang Song, Wenhua Liu, Qingguang Yu, Xiaorong Xie and Zhong-hong Wang, "A neutral-point potential balancing algorithm for three-level NPC inverters using analytically injected zero-sequence voltage," Eighteenth Annual IEEE Applied Power Electronics Confer-ence and Exposition, 2003. APEC '03., Miami Beach, FL, USA, 2003, pp. 228-233 vol.1, doi: 10.1109/APEC.2003.1179220.
    [24] N. Celanovic and D. Boroyevich, "A comprehensive study of neu-tral-point voltage balancing problem in three-level neu-tral-point-clamped voltage source PWM inverters," in IEEE Transac-tions on Power Electronics, vol. 15, no. 2, pp. 242-249, March 2000, doi: 10.1109/63.838096.
    [25] TOSHIBA INTERNATIONAL CORPORATION. (2008). G9000 Un-interruptible Power Supply Multi-level PWM IGBT Technology. Re-trieved from https://www.toshiba.com/tic/datafiles/ups/UPSG9000WP081201_G
    9000_White_Paper_-_multi-level_converter_63.pdf
    [26] G. Carrara, S. Gardella, M. Marchesoni, R. Salutari and G. Sciutto, "A new multilevel PWM method: a theoretical analysis," in IEEE Transac-tions on Power Electronics, vol. 7, no. 3, pp. 497-505, July 1992, doi: 10.1109/63.145137.

    [27] J. A. Houldsworth and D. A. Grant, "The Use of Harmonic Distortion to Increase the Output Voltage of a Three-Phase PWM Inverter," in IEEE Transactions on Industry Applications, vol. IA-20, no. 5, pp. 1224-1228, Sept. 1984, doi: 10.1109/TIA.1984.4504587.
    [28] Fang Zheng Peng, "A generalized multilevel inverter topology with self voltage balancing," in IEEE Transactions on Industry Applications, vol. 37, no. 2, pp. 611-618, March-April 2001, doi: 10.1109/28.913728.
    [29] S. Baek, Y. Cho, B. Cho and C. Hong, "Performance Comparison Between Two-Level and Three-Level SiC-Based VFD Applications With Output Filters," in IEEE Transactions on Industry Applications, vol. 55, no. 5, pp. 4770-4779, Sept.-Oct. 2019, doi: 10.1109/TIA.2019.2920360.
    [30] A. M. Hava, R. J. Kerkman and T. A. Lipo, "Simple analytical and graphical methods for carrier-based PWM-VSI drives," in IEEE Trans-actions on Power Electronics, vol. 14, no. 1, pp. 49-61, Jan. 1999, doi: 10.1109/63.737592.
    [31] 张少伟. SVPWM在有源逆变中的研究与应用 [D]. 华北电力大学(河北), 2009.
    [32] Hart, D. W. (1997). Introduction to power electronics. Upper Saddle River: Prentice Hall.
    [33] S. Ogasawara and H. Akagi, "Analysis of variation of neutral point po-tential in neutral-point-clamped voltage source PWM invert-ers," Conference Record of the 1993 IEEE Industry Applications Con-ference Twenty-Eighth IAS Annual Meeting, Toronto, Ontario, Canada, 1993, pp. 965-970 vol.2, doi: 10.1109/IAS.1993.299015.
    [34] H. Zhang, S. Jon Finney, A. Massoud and B. Wayne Williams, "An SVM Algorithm to Balance the Capacitor Voltages of the Three-Level NPC Active Power Filter," in IEEE Transactions on Power Electronics, vol. 23, no. 6, pp. 2694-2702, Nov. 2008, doi: 10.1109/TPEL.2008.2002820.
    [35] S. An, L. Lai, X. Sun, Y. Zhong, B. Ren and Q. Zhang, "Neutral point voltage-balanced control method based on discontinuous pulse width modulation for a NPC 3-level inverter," 2015 9th International Con-ference on Power Electronics and ECCE Asia (ICPE-ECCE Asia), Seoul, 2015, pp. 2820-2825, doi: 10.1109/ICPE.2015.7168171.
    [36] Vishay Siliconix, "Power MOSFET IRFP450, SiHFP450, " Datasheet.
    [37] X. Wu, G. Tan, Z. Ye, G. Yao, Z. Liu and G. Liu, "Virtual-Space-Vector PWM for a Three-Level Neutral-Point-Clamped Inverter With Unbal-anced DC-Links," in IEEE Transactions on Power Electronics, vol. 33, no. 3, pp. 2630-2642, March 2018, doi: 10.1109/TPEL.2017.2692272.

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