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研究生：	周子晉 Chou, Tzu-Chin
論文名稱：	導線電阻負載效應及輸入偏移對非揮發性記憶體組成的記憶體內運算電路影響之研究 Study of the Interconnect Loading Effect and Input Offset on Computing-In-Memory Circuits with Non-Volatile Memory Devices
指導教授：	江孟學 Chiang, Meng-Hsueh
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 奈米積體電路工程碩士博士學位學程 MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering
論文出版年：	2023
畢業學年度：	111
語文別：	英文
論文頁數：	88
中文關鍵詞：	范紐曼瓶頸、記憶體內運算、非揮發性記憶體、HSPICE 、快閃記憶體、電阻式隨機存取記憶體、導線電阻負載效應、數位類比轉換器偏移
外文關鍵詞：	von Neuman bottleneck, Computing in memory, Non-volatile memory, HSPICE, Flash memory, Resistive random-access memory (RRAM), Wire resistance loading effect, DAC offset
相關次數：	點閱：230 下載：0
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近年來，人工智慧迅速蓬勃發展，對於類神經網路的元件要求也勢必提高。最近
研究指出，目前的功率消耗大多產生在運算單元及記憶體單元的資料傳輸而不是運算，
這現象可稱為范紐曼瓶頸。記憶體內運算是其中一種解決辦法，但由靜態隨機存取記
憶體組成的記憶體內運算的功耗太大，且需要較大面積，所以非揮發性記憶體組
成的記憶體內運算的電路是目前致力研究的項目。另外導線隨著製程進步變得更
細，導致導線電阻增加。若是導線電阻串聯起來，會影響到記憶體內運算的結果，並
導致類比數位轉換器辨別錯誤，這現象可稱為導線電阻的負載效應。接著，因為數位
類比轉換器的輸出電壓會有偏移，這也會影響到記憶體內運算的結果。這篇論文將會
對這兩部分進行討研究與討論。
這篇論文使用快閃記憶體精簡模型以及電阻式隨機存取記憶體的精簡模型，並使
用 HSPICE 模擬軟體探討了導線負載效應及數位類比轉換器的輸出電壓偏移對記憶
體內運算電路所造成的影響。我們從導線電阻負載效應實驗看出，當我們降低讀取電
壓或是改變元件尺寸，可以改善導線電阻負載效應。另外，我們從數位類比轉換器偏
移實驗中，我們使用蒙地卡羅模擬輸入電壓偏移，從模擬結果發現了當我們讀取電壓
降低之後，電流偏移量會變大。所以如果要設計一個記憶體內運算晶片，在準確度、
耗能還有面積三者之中去做取捨是非常重要的。

The rapid growth of artificial intelligence (AI) in recent years has inevitably increased the demand for neural-like network devices. Recent studies have shown that most of the current power consumption is generated in the data transfer of the computational unit and memory unit rather than in the computation, a phenomenon known as the von Neuman bottleneck. Computing-in memory (CIM) is one of the solutions, but the power consumption of in-memory computing consisting of static random-access memory (SRAM) is too large and requires a larger area, so CIM circuits consisting of non-volatile memory are currently being studied. In addition, the wire becomes thinner as the process progresses, increasing the resistance of the wires. If the wire resistances are connected in series, it affects the result of the CIM and causes misidentification, which is called the wire resistance loading effect. Then, because the output of the digital-analog converter has an offset, this also affects the result of the computing-in-memory. These two parts will be discussed in this thesis.
This thesis uses a flash memory compact model and a resistive random access memory compact model, and uses HSPICE simulation software to investigate the effects of wire resistance loading effect and output voltage offset of DAC on the CIM circuit. We have seen from the simulation on the wire resistance loading effect that the wire resistance loading effect can be improved when we reduce the read voltage or change the device size. In addition, we used the Monte Carlo method to simulate the input offset in our digital analog converter offset simulation and found that the current variation becomes larger when we reduce the read voltage. Therefore, if we design a CIM chip, choosing between accuracy, power consumption, and area is very important.

摘要	                                                                                               I
Abstract	                                                                                       II
誌謝	                                                                                               IV
Contents	                                                                                       V
Table Captions	                                                                               VII
Figure Captions	                                                                               VIII
Chapter 1	Introduction	                                                                  1
1	Background	                                                                                  1
2	Motivation  	                                                                                  3
3	Introduction of simulation tools	                                          6
4	Overview of the thesis	                                                          6
Chapter 2	Device Introduction	                                                  8
1	Introduction of non-volatile memory	                                  8
2	Flash	                                                                                          9
2.1 Introduction of flash	                                                          9
2.2 Flash operation principle	                                                10
2.3 The shift of threshold voltage	                                        12
2.4 Read operation	                                                                        12
2.5 Write operation                                                                 	13
2.6 Comparison NOR flash and NAND flash	                        17
3	RRAM	                                                                                        22
3.1 Introduction to RRAM	                                                        22
3.2 Operation and resistance switching mechanism	        23
3.3 Current conduction mechanism of MIM structure	        25
3.4 Ion drift model[32]	                                                                31
Chapter 3	Device Compact Model	                                        33
1	Flash compact model	                                                        33
1.1 PSP model                                                                           	33
1.2 Fundamentals of model theory	                                        34
1.3 Current calculation method	                                                36
2	Flash model calibration	                                                        37
3	RRAM compact model	                                                        40
3.1 Measured data	                                                                        40
3.2 Bilayer RRAM	                                                                        41
3.3 Modeling methodology	                                                        41
4	RRAM model calibration	                                                        45
Chapter 4	Loading Effect of Wire Resistance Discussion	47
1	Wire resistance loading effect of Flash	                                47
1.1 NOR flash circuit design	                                                        47
1.2 Experiment	                                                                                48
1.3 Different read voltage	                                                        50
1.4 Different cell size	                                                                54
2	Wire resistance loading effect of RRAM	                        58
2.1 RRAM CIM cell design	                                                        58
2.2 BL Rwire loading effect and SL Rwire loading effect	60
2.3 Loading effect of single layer and bilayer RRAM	        63
2.4 Different read voltage	                                                        66
3	Summary of wire resistance loading effect	                        68
Chapter 5	Input Offset Discussion	                                        70
1	Experiment	                                                                                70
2	Effect of input offset on NOR flash	                                71
2.1 Monte Carlo simulation for VWL	                                        71
2.2 Monte Carlo simulation for VSL	                                        73
2.3 Monte Carlo simulation for both VWL and VSL	        75
3	Effect of input offset on RRAM	                                        77
3.1 Monte Carlo simulation for VWL	                                        77
3.2 Monte Carlo simulation for VSL	                                        78
3.3 Monte Carlo simulation for both VWL and VSL	        79
4	Summary of input offset	                                                        81
Chapter 6	Conclusion	                                                                82
Chapter 7	Future Work	                                                                84
Reference	                                                                                        85
                                    

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2026-08-31公開

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