近年來，人工智慧的相關技術蓬勃發展，其中的神經網路領域更是被廣泛運用在各個應用，像是影像辨識、物件辨識與語言翻譯等等。為了降低邊緣裝置與雲端的資料傳輸量，近年的趨勢是把AI演算法導入IoT設備，將蒐集到的資料透過AI加速器來執行邊緣運算。另外，為了克服傳統數位加速器的記憶體牆效應，發展出基於記憶體內運算的加速器，藉此避免傳統數位加速器中過多資料搬移的現象，大幅減少功率的消耗與計算的延遲時間。
本論文為採用40奈米製程設計，提出具有能量效益與支援8-bit精準度之乘加運算的8T-SRAM記憶體內運算，透過本論文提出的後級量化機制，減少多餘的電路成本，使面積與功率均能獲得改善。相比於過去的相關文獻，本論文的記憶體內運算架構，在能量效益、運算精準度與操作速度上都具有一定的競爭優勢。

In recent years, artificial intelligence-related technologies have flourished. Among them, the field of neural networks is widely used in various applications, such as image recognition, object recognition, language translation, and so on. In order to reduce the amount of data transmission between edge devices and the cloud, the trend in recent years is to introduce AI algorithms into IoT devices, and use AI accelerators to perform edge computing on the collected data. In addition, in order to overcome the memory wall effect of traditional digital accelerators, several compute-in-memory-based accelerators have been developed to avoid excessive data movement in the traditional digital accelerator. This change may greatly reduce power consumption and calculation delay time.
We proposed an energy-efficient 8T-SRAM-based compute-in-memory macro using 40nm process. Through the backend quantization mechanism proposed in this thesis, both area and power can be reduced. When compared with related works in recent years, the proposed compute-in-memory architecture has competitive advantages in terms of energy efficiency, computing accuracy, and operating speed.

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