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研究生：	黃富民 Huang, Fu-Min
論文名稱：	支援動態存取排程與預充電策略的先進記憶體控制器 An Aggressive Memory Controller with Dynamic Access Scheduling and Bank Precharge Strategies
指導教授：	陳中和 Chen, Chung-Ho
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2004
畢業學年度：	92
語文別：	中文
論文頁數：	63
中文關鍵詞：	記憶體存取排程
外文關鍵詞：	MPEG4 bus arbitration, low power design, bank precharge, memory access scheduling
相關次數：	點閱：89 下載：1
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隨著半導體製程的進步，處理器的時脈日漸提升，使得記憶體系統的頻寬將成為SoC 系統效能的瓶頸。在這篇論文裡，我們提出了動態記憶體存取排程和預充電策略兩個機制來針對DRAM 的存取動作改善。整個論文的實驗環境是以verilog 硬體描述語言建立而成，主要目的是建立MPEG4 壓縮的流程，模擬整個系統對匯流排和記憶體的存取行為。
動態記憶體排程機制是利用位於記憶體控制器中的資訊，來提升row-hit的機率，減少不必要的ACTIVE-PRECHARGE 所造成的負擔；early precharge 機
制透過匯流排仲裁器的幫助，減少SDRAM 中active bank 的cycle 數，降低DRAM 的背景耗電量。實驗模擬的結果顯示出，同時整合本論文所提出的動態記憶體排程與early precharge 兩個機制的情況能有最佳的energy-delay 乘積，配合不同的仲裁策略，與操作在傳統close page policy 下的情況相比，降低了約29~46個百分比，有效節省電源的消耗。

System performance becomes increasingly limited by memory bandwidth in contemporary System-on-Chip designs. In this thesis, we present memory access scheduling and bank precharge strategies for current DRAM operations. The simulated system models an MPEG4 encoding process in Verilog hardware description language.
The memory access scheduling explores the available information in the memory controller to improve the row-hit rate. An early bank precharge scheme effectively reduces the number of active bank cycles. Simulation results show that the
dynamic access scheduling scheme integrated with the early precharge strategy achieves the best energy-delay product among various arbitration schemes evaluated, 29%~46% less than operating under conventional close page mode.

中文摘要........................................　
英文摘要........................................　
誌謝............................................　
目錄............................................
表目錄..........................................
圖目錄..........................................
Chapter 1 序論.................................1
1 研究動機...................................1
2 研究貢獻...................................2
3 內容編排...................................2
Chapter 2 背景知識.............................3
1 Arbiter 的相關知識.........................3
1.1 Arbiter 的基本簡介.......................3
1.2 數種arbitration scheme 的比較............4
2 SDRAM 的相關知識...........................6
2.1 SDRAM 基本簡介...........................6
2.2 SDRAM 的接腳與結構.......................7
2.3 SDRAM command 的介紹....................10
2.4 SDRAM mode control register 設定........12
2.5 如何對SDRAM 做存取......................12
2.6 SDRAM 的電子特性........................15
2.7 SDRAM 各種狀態下的耗電量................16
3 SDRAM controller 對記憶體的bank active 
管理方式......................................18
3.1 Close page policy.......................18
3.2 Open page policy........................19
4 SDRAM 耗電量的估計方法....................20
Chapter 3 研究議題............................25
1 動態記憶體排程............................25
1.1 雙重動態優先權提升......................26
1.2 位址的預測..............................27
1.3 減少row miss 次數對SDRAM 耗電量的影響...28
2 進階的SDRAM PRECHARGE策略(early precharge)28
2.1 改善系統的執行效能......................28
2.2 降低bank active cycle 數................29
2.2.1 一般情形下任意的SDRAM 存取............30
2.2.2 妥善記憶體配置下的SDRAM 存取..........31
2.2.3 配合動態記憶體排程的SDRAM 存取........31
2.3 Early precharge 對耗電量的影響..........32
Chapter 4 環境建立............................34
1 MPEG4 encoding 系統之介紹.................34
2 系統上各個device behavior model 的建立....37
2.1 Video In (VI)...........................37
2.2 Motion Estimation & Discrete Cosine 
Transform (ME/DCT)............................38
2.3 AC/DC Prediction (AC/DC)................39
2.4 Variable Length Coding (VLC)............40
Chapter 5 實驗結果............................42
1 效能上的提升..............................42
1.1 降低row miss 次數.......................42
1.2 對系統執行時間的影響....................43
2 SDRAM 耗電量的節約........................45
2.1 SDRAM bank active cycle 數的比較........45
2.2 合併兩種技術來改善SDRAM 的耗電量........46
2.2.1 改善SDRAM 的背景耗電量................47
2.2.2 減少因ACTIVE-PRECHARGE 造成的耗電量...48
2.2.3 改善SDRAM 的整體耗電量................49
Chapter 6 結論................................51
參考文獻......................................52
附錄A 自述....................................54
附錄B 英文論文................................55
                                    

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[13] AMBA Specification Rev 2.0.
[14] AMBA University Kit, Technical Reference Manual.
[15] PHILIPS PNX1300 Series Media Processors Data Book.
[16] Micron Technical Note TN-46-03 “Calculating Memory System Power
for DDR＂.
[17] Micron Technical Note TN-47-04 “Calculating Memory System Power
for DDR2＂.
[18] Micron 64Mb SDRAM Data Sheet “MT48LC4M16A2＂.
[19] Micron 64Mb SDRAM Simulation Model “MT48LC4M16A2＂.
[20] Samsung SDRAM 64Mb H-die (x4, x8, x16) Data Sheet.
[21] Winbond 64 Mb SDRAM Data Sheet “W986416DH＂.

校內：2005-09-07公開
校外：2006-09-07公開

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