電源管理晶片從電壓模式控制發展到漣波控制，漣波控制具有比傳統電壓模式控制及電流模式控制快速的暫態響應，因此廣泛的應用在電源管理晶片中，以研究漣波控制為目標，本論文的研究脈絡從數位電壓模式控制延伸到類比及數位漣波控制，並聚焦在降壓型電源轉換器晶片設計與實現，在本論文提出了兩個數位電壓模式控制的系統，三個系統漣波控制分別針對類比的遲滯控制及數位的固定導通時間控制進行研究與實作。
數位電壓模式控制研究與實作方面，本論文中提出的第一個系統為具有堆疊式功率級之數位單相降壓型電源轉換器，為了讓3.3伏特耐壓的功率元件操作在2.7伏特到4.2伏特鋰電池的輸出下，採用了堆疊式功率級，並提出適應性的偏壓電路來優化效率，與傳統堆疊式功率級偏壓方式相比能有效提升23%效率；本論文中提出的第二個系統為具有電流平衡及溫度平衡的數位電壓模式控制多相電源轉換器，提出了不透過電流及溫度感測元件取得電流及溫度資訊，透過直接調整控制器實現準確的電流平衡及溫度平衡。
漣波控制研究與實作方面，本論文中提出的第一個系統為基於鎖相迴路控制的固定切換頻率準V2類比遲滯控制降壓型電源轉換器。透過鎖相迴路控制遲滯視窗此系統能使切換頻率不隨輸入電壓及負載電流變化，在低電流負載的情況下可以操作在頻率脈波調變的模式下降低切換損失，提升電源轉換效率，此外，利用準V2架構取得電感電流資訊以降低輸出電壓漣波。量測結果中，此系統可以操作在18到700毫安培的負載電流範圍，2.7伏特到4.2伏特的輸入電壓範圍，及1.2伏特的輸出電壓，透過鎖相迴路切換頻率能鎖定在1 MHz，5微秒的負載電流暫態響應及最高95.6%的電源轉換效率；提出的第二個系統為具有適應性電壓位準技術及自動校正技術之數位V2固定導通時間控制降壓型電源轉換器。適應性電壓位準技術透過適應性電壓位準視窗可以實現快速的暫態響應，此外，透過自動校正技術能使得適應性電壓位準技術的效果不隨著功率級元件的老化或變異而改變。此系統的晶片是透過90奈米CMOS 製程實現，系統中數位控制器皆由數位標準元件庫的元件實現。晶片量測結果中，在0.9安培負載步階下，輸出電壓能夠有效控制在1.1伏特上110毫伏特的適應性電壓位準視窗中；提出的第三個系統為具有輸出電壓偏移校正技術以之數位電流模式固定導通時間控制降壓型電源轉換器。電流模式固定導通時間控制能實現快速暫態響應，為了以全數位化方式實現，此系統電壓及電流迴路皆使用全數位方式實現，由於電流模式固定導通時間控制先天具有受電流漣波影響的輸出電壓準位偏移，輸出電壓偏移校正技術能使得輸出電壓在全負載範圍中皆能準確被調節在參考電壓上，此系統的晶片是透過0.18微米CMOS 製程實現，系統中數位控制器也是皆由數位標準元件庫的元件實現。晶片量測結果中，透過所提出的全數位輸出電壓偏移校正技術，全負載範圍下輸出電壓偏移為2%。另外一方面輸出電壓暫態在2.5安培負載變化下僅有100毫伏特變化。

The control methodology of power management IC (PMIC) develops from voltage mode control to ripple-based control. Ripple based control can achieve better transient response performance than traditional voltage mode and current mode control which makes it widely adopted on PMIC nowadays. To investigate ripple-based control, this dissertation starts from the digital voltage mode control and then aimed analog and digital ripple-based control. Focus on the design and implementation buck converter integrated circuit (IC). Two digital voltage mode control systems and three ripple-based control targets on analog hysteretic control and digital constant on-time control respectively systems are proposed in this dissertation.
In term of the research and design of voltage-mode control, the first system proposed in this dissertation is a digital buck converter with adaptive driving circuit for cascode power MOS. To withstand 2.7V-4.2V Li-ion battery voltage stress with 3.3V power MOS, cascode structure is implemented. Moreover, an adaptive driving circuit is proposed to optimize the conversion efficiency. Comparing to tradition driving circuit, the proposed circuit can improve efficiency with 23% maximum; the second system proposed in this dissertation is a digital multiphase converter with sensor-less current and thermal balance mechanism. The current and thermal balance mechanism is realized without current and thermal sensor. According to the measurement result, the current and thermal can be well control with proposed mechanism.
In term of the research and design of ripple-based control, the first system proposed in this dissertation is a fixed-frequency quasi-V2 hysteretic buck converter with PLL-based two-stage adaptive window control. The proposed converter can achieve fixed frequency switching through a novel phase-locked-loop-based two-stage adaptive window control. Under ultralight load conditions, the proposed converter operates in a pulse frequency modulation mode to reduce the switching loss and improve light load efficiency. A quasi-V2 technique is applied for obtaining inductor current information to reduce output voltage ripple. The experimental results show that the proposed converter can operate at a load current ranging from 18 to 700 mA, a supply voltage ranging from 2.7 to 4.2 V, and an output voltage of 1.2 V. Through the PLL control, the switching frequency is maintained at 1 MHz. The transient response time is approximately 5 μs, and the highest efficiency registered is 95.6%; the second system proposed in this dissertation is digital V2 COT control buck converter with adaptive voltage positioning (AVP) and automatic calibration mechanism. AVP mechanism is able to achieve fast load current transient with the margin of AVP window. And, the automatic calibration for AVP mechanism can guarantee that the performance of AVP is not impact with aging and variation on power stage component. A prototype chip is fabricated using a 90-nm CMOS process. The digital controller is fully realized using a standard cell library. Under a 0.9-A load transient, the measured output voltage can be adequately constrained within a specified 1.1-V and 110-mV AVP window; the third system proposed in this dissertation is fully digital current mode COT control buck converter with output voltage offset cancellation mechanism. Current mode COT can achieve fast transient response and low output voltage ripple with additional current path. To fully digitalize the control loop in this work, both current mode control and the additional current path are implemented in digital way. However, the current path may induce inevitable output voltage offset. To ensure effective output voltage regulation within all load current ranges, an output voltage offset cancellation mechanism is proposed. A prototype converter is fabricated using 0.18-μm CMOS process technology. The controller is fully implemented as a standard-cell-based digital circuit. Measurement results indicates the output voltage regulation in full-load range was 2%, and 100 mV output voltage overshoot under 2.5A load transient response.

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