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研究生: 姚冠伸
Yao, Guan-Shen
論文名稱: 極低功耗物聯網SoC應用之降壓型轉換器研究與設計
Study and Design of Buck Converter for Ultra-Low Power IoT SoC Application
指導教授: 蔡建泓
Tsai, Chien-Hung
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2020
畢業學年度: 108
語文別: 中文
論文頁數: 86
中文關鍵詞: 極低功耗物聯網降壓型轉換器輸出電壓品質偏壓自動調變
外文關鍵詞: Ultra low power, IoT, Buck Converter, output voltage quality, automatic bias adjustment
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  • 本論文提出具偏壓自動調變之極低功耗降壓型轉換器,主要克服的議題是當系統操作在極低電流下,電路效能將大打折扣,因此電源轉換器的輸出電壓品質勢必大幅下降。相對於其他實現方式,本論文利用電路架構特性,在不需額外資訊(如負載大小或負載變化時機等)的前提下,便能自動調變偏壓電流使得電路在輕載以極低靜態電流操作並滿足重載時所需之效能。
    本作品使用TSMC 0.18um 1.8V/3.3V 1P6M Mixed Signal製程進行晶片設計。在晶片量測結果上,本作品實現靜態電流僅為186nA,且在全負載範圍內皆可滿足輸出電壓漣波±3%內,而輸入電壓、輸出電壓的規格亦滿足現今物聯網SoC之應用。

    An ultra low power buck converter with automatic bias adjustment is proposed. The main problem to overcome is that when the system is operated at very low current, the circuit performance will be greatly reduced, so the output voltage quality of the buck converter will be greatly decline. Compared with other papers, this work uses the characteristics of the circuit architecture to automatically adjust the bias current without additional information (such as load or the timing when load is changing, etc.) and the circuit achieves a very low quiescent current at light loads and meet the specification during heavy load.
    This work uses TSMC 0.18um 1.8V/3.3V 1P6M Mixed Signal process for chip design. On the chip measurement results, the quiescent current of this work is only 186nA, and it can meet the output voltage ripple within ±3% specification in the full load range, and the input voltage and output voltage specifications also meet the application of today's IoT SoC .

    摘要 III 目錄 VIII 圖目錄 X 表目錄 XIV 1 第一章 緒論 1 1.1. 研究動機 1 1.2. 目標與貢獻 3 1.3. 論文架構簡介 4 2 第二章 切換式降壓型轉換器控制技術 5 2.1. 脈波寬度調變控制 5 2.1.1. 電壓模式控制 5 2.1.2. 峰值電流模式控制 6 2.1.3. 比較與討論 9 2.2. 漣波控制 10 2.2.1. 遲滯控制 10 2.2.2. 固定導通/固定不導通時間控制 16 2.2.3. 比較與討論 20 2.3. 物聯網應用之主要規格 21 2.3.1. 輸出電壓漣波 21 2.3.2. 靜態電流 22 2.3.3. 轉換效率 22 3 第三章 具極低功耗之降壓型轉換器 24 3.1. 業界文獻研究現況 24 3.2. 學界文獻研究現況 37 3.3. 比較與討論 48 4 第四章 具偏壓自動調變之極低功耗降壓型轉換器 50 4.1. 目標與應用 50 4.2. 規格與架構 50 4.3. 功率級設計 52 4.4. 比較器設計 54 4.4.1. Adaptive-Bias比較器 54 4.4.2. Power-Gated比較器 58 4.5. Controller與Driver設計 59 5 第五章 晶片實作與量測驗證 60 5.1. 晶片設計流程與系統建模 60 5.1.1. 類比電路Top-down設計流程 60 5.1.2. 系統建模 62 5.2. 晶片佈局考量與規則 65 5.3. 全晶片後模擬結果 68 5.4. 量測規劃與量測環境 72 5.5. 量測結果 75 5.6. 成果比較與討論 79 6 第六章 結論及展望 81 6.1. 總結與貢獻 81 6.2. 未來工作與研究方向 81 參考文獻 83

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