動態二進制碼轉譯(Dynamic Binary Translation) 的技術，可以用來轉譯已經編譯成給特定處理器架構的二進制碼（或稱作機械碼），成為另一種處理器架構所規範的二進制碼。由於軟體相容性的問題延緩了新的處理器架構和微架構的採用，舊的指令集架構(Instruction Set Architecture)沒辦法很快地被取代掉。將程式碼由舊的指令集架構轉移到新的指令架構又相當地耗費時間。而動態二進制碼轉譯則提供了一種自動轉譯的機制，不需要事先改變已經編譯給舊的指令集架構的二進制碼，直接由動態轉譯機制轉譯並執行。Transmeta Crusoe和IBM DAISY提供了兩個成功的範例，它們各自在自己新設計的VLIW處理器上轉譯了不同的系統：Crusoe轉譯並模擬了x86 IA-32的指令及架構，而DAISY則轉譯了來自PowerPC的架構。

在本篇論文中，我們提出了一個結合動態二進制碼轉譯技術和多執行緒處理器特點的架構。這個架構的主要目的是提供一個雙執行緒二進制碼轉譯(Dual-threaded Binary Translation)的機制，在一個類似MIPS的雙執行緒微處理器模擬平台上轉譯並執行已經編譯成x86 IA-32的二進制程式碼。在這個雙執行緒處理器的模型中，一條叫做Translation的執行緒，負責轉譯由x86程式而來的來源指令，成為可以在目的處理器執行的目的指令群。另外一條稱作Execution的執行緒，則負責執行轉譯過後的二進制碼。除此之外，執行緒同步的輔助機制則用來管控切換硬體資源給這兩個執行緒的時機，以及負責在兩個執行緒間傳遞轉譯過程中所需的資訊。為了減少在同步機制上所花費的時間，同步機制中整合了一個窺控(Snooper)的硬體來增進效能。轉譯的快取記憶體(Translation Cache) 的概念則被實現成一個以區塊為單位的快取硬體和一個選擇性的軟體快取記憶體架構。為了提升整體模擬系統的效能，論文中亦分析了各個硬體快取記憶體的結構和跳躍預測器對效能的影響。

Dynamic binary translation is a technology that translates executable machine code, also called binary code, from original Instruction Set Architecture (ISA) to the machine code of another ISA on the fly. Because software compatibility slows the adoption of new processor architectures and micro-architecture, old ISA can’t be replaced easily. Porting code from one ISA to another is also time-consuming. Dynamic binary translation offers a solution for automatically converting binary code of legacy architecture to run on a new ISA without re-porting the source code. Transmeta Crusoe and IBM DAISY provide the successful examples of binary translation in their own VLIW processors. One emulates the x86 IA-32 system and the other emulates the POWER PC machine.

In this thesis, we propose a mechanism that combines the ideas of dynamic binary translation and features of multithreaded processor. A dual-threaded binary translation (DT-BT) mechanism is implemented to execute the x86 IA-32 binary programs on a dual-threaded MIPS-like microprocessor simulator. One thread in this dual-threaded processor, called translation thread, is responsible for translating the source instructions form x86 programs. The other thread, called execution thread, takes charge of executing translated binary code. Besides, a synchronization mechanism is implemented to transfer translation information (including translation request, response and translated result) and switches hardware resource between these two threads. A snooping hardware is integrated with the synchronization mechanism to eliminate the synchronization overhead. The concept of translation cache in this BT-BT model is implemented as a block-based hardware cache and an optional software cache. The influence of each organization of hardware cache and BTB predictor is analyzed to achieve high emulation performance.

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