高解析度的液晶顯示源極驅動電路面臨到數位類比轉換器面積過大和輸出緩衝器偏移電壓等問題，因此本論文提出了一應用於十位元液晶顯示源極驅動電路之低面積數位類比轉換器以及一具有低偏移電壓之輸出緩衝器。
十位元數位類比轉換器採用了電阻串-電容兩級式的架構，相較於傳統的單級電阻串架構，有較小的佈局面積。輸出緩衝器採用了改良自傳統CLASS-A兩級式放大器的架構，由於傳統CLASS-A兩級式放大器依據其輸入差動對的形式(PMOS或NMOS)，其輸出級僅具有充電或放電能力，不適用於較低功率的驅動模式(如2-dot 反轉模式)，因此本論文利用一個電流正回授的路徑改善傳統CLASS-A兩級式放大器輸出級的充電(放電)能力，使其適用於低功率的操作模式；在輸出緩衝器偏移電壓部份，採用了平均偏移電壓的方式，利用數個開關以及一個控制訊號，週期性的改變偏移電壓的極性，使偏移電壓於緩衝器輸出端呈現平均的效果，此法不需要額外的儲存電容，相當的節省成本。
採用TSMC 0.35μm 2P4M CMOS製程下線，整體晶片面積為1704 x 262 μm2。量測的輸出緩衝器穩定時間均小於7.8μs，平均後的最大偏移電壓為0.57LSB，最大的DNL和INL分別為3.09LSB和5.69LSB。

The area of a DAC and the offset of a buffer are the main issues to be resolved for high resolution source drivers. In this thesis, area-efficient R-C DACs with low-offset push-pull output buffers for a 10-bit source driver are proposed.
The 10-bit R-C DAC adopts a two-stage structure, which composes of a R-string and a weighted capacitor array. Comparing to a conventional 10-bit R DAC, the 10-bit R-C DAC has a smaller area. The output buffer adopts a modified opamp, based on a conventional two-stage Class-A opamp. A conventional Class-A opamp only has a charge or a discharge ability according to its type of input differential pair so it is not suitable for a low power driving mode (e.g. two-dot inversion). Therefore, a positive current feedback path is used to improve the insufficient charge (discharge) ability of a conventional two-stage Class-A opamp so that it is suitable for a low power driving mode. An offset averaging method is used for the offset of the output buffer. By using several switches and a control signal, the polarity of the offset is reversed periodically so the offset is averaged at the output of the output buffer. The offset averaging method needs no extra capacitors so it is cost-effective.
The chip is fabricated using the TSMC 0.35μm 2P4M CMOS process and its area is 1704 x 262 μm2. The measured settling time of the output buffer is under 7.8μs. The maximum offset after averaging is 0.57LSB. The maximum DNL and INL are 3.09LSB and 5.69LSB respectively.

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