本論文為應用於2.4 GHz ISM band的非整數型鎖相迴路電路設計，內容可分為兩個部分：第一部分為鎖相迴路的其中一個子電路，壓控振盪器的設計；第二部分為完整的非整數型鎖相迴路。在本論文所設計之兩個電路皆使用 TSMC 0.18 µm CMOS製程設計實現。
在第一部分壓控振盪器採用差動式可切換IMOS變容器並加入開關方式提高容值變化範圍，進而使壓控振盪器的頻率可調範圍增加。容值在模擬結果變化範圍為 0.3 pf ~ 0.95 pf。在本次設計電路之量測頻率變化範圍為2.625 GHz~1.94 GHz (30%)；相位雜訊在頻率偏移1MHz處的最佳表現為 -121 dBc/Hz；整體輸出功率皆大於 -12 dBm；功率消耗為6.6mW。包含緩衝放大器之整體晶片面積為0.75 mm2。
在第二部分2.4 GHz非整數型鎖相迴路中，子電路包含相位頻率偵測器(PFD)、充電泵(CP)、迴路低通濾波器(LPF)、壓控振盪器(VCO)、多模數除頻器(MMD)及三角積分調變器(SDM)。藉由三角積分調變器控制多模數除頻器除數，在一段時間內除數的變化達到平均為除非整數的功能，並有頻帶不受參考頻率的限制、較小的鎖定時間、較佳的相位雜訊表現等優點。在本次設計電路之量測參考頻率為18.75 MHz，操作頻率為2.4 GHz ~ 2.521 GHz；相位雜訊在頻率偏移 1 MHz處的最佳表現為 -96.8 dBc/Hz，整體皆小 於-85 dBc/Hz；輸出功率皆大於2 dBm；整體功率消耗為9.36 mW。包含緩衝放大器之整體晶片面積為1.81 mm2。

This thesis proposes a fractional-N phase-locked loop circuit applied to the 2.4 GHz ISM band. The content can be divided into two parts: the first part is the design of one of PLL's sub-circuits, the voltage-controlled oscillator, and the second part is a complete 2.4 GHz fractional phase-locked loop. These two circuits are both fabricated by TSMC’s 0.18 µm COMS technology.
In the first part, the VCO design, an Inversion-MOS (IMOS)-based varactor is used, which is connected differentially and uses switches to increase the range of capacitance. Such design methodology can increase the tuning range of the VCO. The capacitance is from 0.3 pf to 0.95 pf in the simulation results. The measurement of tuning range of VCO is 2.625 GHz~1.94 GHz (30%).The best performance of phase noise is -121 dBc/Hz at 1 MHz frequency offset. Output power is greater than -12 dBm. Power consumption is 6.6 mW. The total chip size including buffer amplifier and pads is 0.75 mm2.
In the second part, the 2.4 GHz fractional-N PLL design, its sub-circuits include a phase frequency detector, a charge pump, a loop low pass filter, a voltage-controlled oscillator, a multi-modulus divider and a delta-sigma modulator. By dithering the division ratio, a fractional divider is implemented, which has the advantages of not-reference-frequency-limited, less locking time, and better phase noise performance. The reference frequency is set to 18.75 MHz, and the operating frequency range is from 2.4 GHz to 2.521 GHz.The best performance of phase noise is -96.8 dBc/Hz at 1 MHz frequency offset, and the overall phase noise performance is less than -85 dBc /Hz. Output power is greater than 2 dBm. Overall power consumption is 9.36 mW. The total chip size including buffer amplifier and pads is 1.81 mm2.

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