在本論文中，我們實現一個操作在88-96 GHz的毫米波壓控振盪器晶片設計及提出一個94 GHz鎖相迴路頻率合成器模擬設計。論文第一部分為了提升毫米波壓控振盪器的頻率可調範圍，提出Inductance-Compensated Capacitive Source Degeneration (IC-CSD)技巧，於交互耦合對之源極設計一電感，利用電感補償改良已知的CSD技術，並達到提升毫米波壓控振盪器的頻率可調範圍的目的。晶片採用TSMC CMOS 90-nm GUTM製程，電路設計使用Agilent ADS與3-D全波電磁模擬軟體進行模擬，毫米波晶片量測採fully on-wafer方式進行量測。論文第二部分提出一個94 GHz鎖相迴路頻率合成器模擬設計，包含相頻偵測器(PFD)、充電泵(CP)、迴路濾波器(LPF)、壓控振盪器(VCO)、注入鎖定除頻器(ILFD)及除頻鍊，並實作其中的振盪器與注入鎖定除頻器毫米波晶片。鎖相迴路設計中，振盪器採用倍頻技巧，使得迴路中的最高頻率僅需操作在輸出頻率的一半，以降低鎖相迴路中，子電路的設計負擔，且利用振盪器的Gate-Tuning技巧，達到鎖相迴路調整頻率的表現，以涵蓋變異造成的輸出頻率飄移，可應用於W-Band無線收發機系統，提供穩定的本地振盪源。

This thesis presents a chip design of a wideband voltage-controlled oscillator (VCO) operating at 88 GHz to 96 GHz and a simulation design of a 94-GHz phase-locked loop (PLL).
In the first part, this thesis proposes the inductance-compensated capacitive source degeneration (IC-CSD) technique for improvement of frequency tuning range. Frequency tuning range can be boosted by the proposed IC-CSD technique which uses inductive compensation to improve conventional crossed-coupled pair with capacitive source degeneration (CSD) technique. Fabricated in 90-nm CMOS technology, the measured VCO based on the proposed technique achieves a tunning range of 8.7% (from 88 to 96 GHz). From the experimental results at 94 GHz, the maximum output power is +5.2 dBm. The phase noise are -71.7 dBc/Hz and -96.5 dBc/Hz, at 1-MHz and 10-MHz frequency offset, respectively. This chip integrated with a VCO core and a drive amplifier dissipates a total power consumption of 85 mW, where the VCO core consumes 30.36 mW from a 1.2-V supply. The chip area is 0.63×0.4 mm2.
In the second part, the simulation design of a 94-GHz integer-N PLL including a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF), a VCO, an injection-locked frequency divider (ILFD) and a divider chain is presented. The VCO and ILFD for the proposed 94-GHz PLL were fabricated in 90-nm CMOS technology for verification. Since high-speed analog building blocks of the mm-wave frequency synthesizer suffers from parasitic loss burden, the proposed PLL utilizes the second harmonic output frequency of VCO so that the maximum frequency in the loop can be at the half of the output frequency in 94-GHz band. To cover the frequency drift caused by process voltage temperature (PVT) variation, a mm-wave frequency synthesizer adopts the VCO using the gate-tuning technique. The post-simulation of this PLL circuit in 90-nm CMOS process shows that the PLL is locked at the output frequency of 94 GHz with the input reference frequency is 78.3 MHz. The total power dissipation of PLL is 81.43 mW for a supply of 1 V. The proposed PLL occupies the chip area of 1.75×0.73 mm2. The presented frequency synthesizer is applicable to the W-band wireless transceivers as a local oscillator (LO).

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