本論文提出使用SystemVerilog作為混層式Top-down設計方法中類比行為模型層級使用語法。其相較於傳統以Verilog-A語法建立類比行為模型方式，能於保留精確度下，縮短57%模擬時間。
於混層式Top-down設計方法中，設計初期使用SystemVerilog建立類比及數位電路行為模型，經由頂層驗證確認過各子電路規格後，類比電路依照行為模型規格設計電晶體層級之電路；數位電路根據SystemVerilog行為模型所建立之功能撰寫Verilog等硬體描述語言，再透過數位合成軟體將Verilog等硬體描述語言合成為電晶體層級電路，待完成類比及數位電晶體層級設計後，進行佈局設計並整合於相同晶片中，驗證全系統正確且符合規格後即可進行下線。
本論文以台積電0.18μm 1P6M Mixed Signal製程實作一降壓型轉換器晶片，晶片面積佔4.41mm2，操作於輸入電壓3.3V/輸出電壓1.2V及抽載電流100mA-500mA間，透過晶片實作方式驗證本論文之混層式Top-down設計方法。

In this paper, we propose a mixed-level top-down design methodology based on SystemVerilog behavior model. Compared with the traditional mixed-level top-down design methodology based on Verilog-A behavior model, it can save the simulation time by 57% with accuracy maintaining. We design a digitally-controlled buck converter based on this design methodology for portable devices application. This chip was manufactured by TSMC 0.18-um CMOS process technology. Buck converter circuit was integrated in the chip except the discrete components such as inductor and capacitance.
In the beginning of the mixed-level top-down design methodology, SystemVerilog is used to create analog and digital circuit behavior models. By simulating top-level behavior model, we can define the specifications of each sub-circuit. After the specification of each sub-circuit is chosen, we design the analog transistor-level circuits according to the analog behavior-level specifications. We write the RTL code such as Verilog code according to the digital behavior-level specifications and further synthesis to transistor-level. While all sub-circuits are transferred to the transistor level, we verify the results of the system and check if the simulation results will meet the specifications.
This design methodology can avoid re-design sub-circuit transistor-level circuit when error happened after simulation of top-level transistor circuits.

[1]K. Kundert and H.Chang, "Top-Down Design and Verification of Mixed-Signal Circuits, "[Online].Available: https://designers-guide.com/docs/tddv.pdf
[2]K. Kundert, "Principles of Top-Down mixed-signal design, "[Online].Available: https://designers-guide.org/design/tdd-principles.pdf
[3]K. Kundert, H. Chang, D. Jefferies, G. Lamant, E. Malavasi and F. Sendig, "Design of mixed-signal systems-on-a-chip," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 12, pp. 1561-1571, Dec. 2000.
[4]K. Kundert "A formal Top-down design process for mixed-signal circuits, " presented at the Electronic Design Processes Workshop, Monterey, CA, USA, 2001.
[5]M. S. McCorquodale, F. H. Gebara, K. L. Kraver, E. D. Marsman, R. M. Senger and R. B. Brown, "A Top-down microsystems design methodology and associated challenges," 2003 Design, Automation and Test in Europe Conference and Exhibition, Munich, Germany, 2003, pp. 292-296.
[6]E. Chou and B. Sheu, "Nanometer mixed-signal system-on-a-chip design," in IEEE Circuits and Devices Magazine, vol. 18, no. 4, pp. 7-17, July 2002.
[7]I. Miller and A. Ferreira-Noullet, "Behavioral modeling in industrial IC design experiences and observations," in Proceedings of the 2004 IEEE International Behavioral Modeling and Simulation Conference, 2004. BMAS 2004., 2004, pp. 37-40.
[8]L. Laguna, R. Prieto, J. Oliver, and J. Cobos, "Top-down methodology employing hardware description languages (HDLs) for designing digital control in power converters," in 2008 11th IEEE International Power Electronics Congress, 2008, pp. 133-137.
[9]P. Jalas and T. Rahkonen, "Estimating the Impact of Methodology on Analog Integrated Circuit Design Time," in IEEE Design & Test, vol. 34, no. 1, pp. 35-46, Feb. 2017, doi: 10.1109/MDAT.2015.2497331.
[10]K. Kundert and H. Chang, "Model-based functional verification," Design Automation Conference, Anaheim, CA, 2010, pp. 421-424, doi: 10.1145/1837274.1837380.
[11]K. Kundert and H. Chang, "Verifying all of an SOC-analog circuitry included," in IEEE Solid-State Circuits Magazine, vol. 1, no. 4, pp. 26-32, Fall 2009, doi: 10.1109/MSSC.2009.933430.
[12]Mehta, Ashok B. "Analog/mixed signal (ams) verification." ASIC/SoC Functional Design Verification. Springer, Cham, 2018. 255-271.
[13]K. Karnane, S. Balasubramanian “Solutions for Mixed-Signal SoC Verification”, Cadence Design,2012
[14]S. Balasubramanian and P. Hardee, "Solutions for Mixed-Signal SoC Verification Using Real Number Models, " Cadence Design Systems, 2013.
[15]“Verilog-AMS Language Reference Manual“, 2014, [Online] Available: https://accellera.org/images/downloads/standards/v-ams/VAMS-LRM-2-4.pdf
[16]J. Chen,M. Henrie,M.F.Mar and M.Nizic, "Mixed-Signal Methodology Guide" Lulu.com, 2012,pp 32-41.
[17]G. Gal, O. A. Fattah and G. W. Roberts, "A 30–40 GHz fractional-N frequency synthesizer development using a Verilog-A high-level design methodology," 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), Boise, ID, 2012, pp. 57-60, doi: 10.1109/MWSCAS.2012.6291956.
[18]C. Pao, Y. Chen and C. Tsai, "Top-down methodology based low-dropout regulator design using Verilog-A," 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Guilin, 2014, pp. 1-3, doi: 10.1109/ICSICT.2014.7021500.
[19]N. Georgoulopoulos and A. Hatzopoulos, "Real number modeling of a Flash ADC using SystemVerilog," 2017 Panhellenic Conference on Electronics and Telecommunications (PACET), Xanthi, 2017, pp. 1-4.
[20]“Verilog-A Reference Manual“, 2004, [Online] Available: https://literature.cdn.keysight.com/litweb/pdf/ads2004a/pdf/verilogaref.pdf
[21]H. Thibieroz,A. Khan, and D. Cronauer, "Extending Digital Verification Techniques for Mixed-Signal SoCs with VCS® AMS," Synopsys,2014
[22]M. Louis, M. Dessouky and A. Salem, "PLL Real Number Modeling in SystemVerilog," 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, 2019, pp. 257-260, doi: 10.1109/SMACD.2019.8795233.
[23]“Verilog-AMS Real Valued Modeling Guide“ Cadence Design Systems, Feb 2016
[24]C. Wegener, "Method of modeling analog circuits in verilog for mixed-signal design simulations," 2013 European Conference on Circuit Theory and Design (ECCTD), Dresden, 2013, pp. 1-5, doi: 10.1109/ECCTD.2013.6662227.
[25]P. Das, J. K. Yadav and S. Deb, "Mixed Mode Simulation and Verification of SSCG PLL through Real Value Modeling," 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), Kolkata, 2016, pp. 591-592, doi: 10.1109/VLSID.2016.110.
[26]P. Das and S. Deb, "Exploration of Real Value Modelling for Complex Mixed Signal Verification.",(2015).[Online].Available:https://pdfs.semanticscholar.org/5902/c8e516e7b459795b4889f0f98214e5761eb1.pdf
[27]N. Georgoulopoulos and A. Hatzopoulos, "Efficiency evaluation of a SystemVerilog-based real number model," 2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST), Thessaloniki, 2018, pp. 1-4.
[28]N. Georgoulopoulos and A. Hatzopoulos, "Design of a Digital PLL Real Number Model Using SystemVerilog," 2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST), Thessaloniki, Greece, 2019, pp. 1-4, doi: 10.1109/MOCAST.2019.8741595.
[29]IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language," in IEEE Std 1800-2017 (Revision of IEEE Std 1800-2012) , vol., no., pp.1-1315, 22 Feb. 2018, doi: 10.1109/IEEESTD.2018.8299595.
[30]A. Caicedo and S. Fritz, "Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation using SystemVerilog User-Defined Nettype",(2019).[Online].Available:https://dvcon-europe.org/sites/dvcon-europe.org/files/08_2_Caicedo_finalpaper_09_16_2019_15_52.pdf
[31]A. Caicedo, "Real-Number Modeling of Loading Effects in Power Regulation using SV EEnet", Cadence User Conference, 2019
[32]R. Vogelsong, "SystemVerilog “EEnet” Nettype Usage and its Application to Voltage Doubler Modeling",Cadence User Conference, 2017
[33]J. Jang, M. Park, D. Lee and J. Kim, "True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example," Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, San Jose, CA, 2012, pp. 1-4.
[34]H. p. Forghani-Zadeh and G. a. Rincon-Mora, "Fast and reliable top-level simulation strategy for mixed-signal integrated circuits and its application to DC-DC converters," IET Circuits, Devices & Systems, vol. 1, no. 2, pp. 143-150, 2007.
[35]Q. Wang, "Mixed-Signal SOC Verification using Analog Behavioral Models.",(2012).[Online].Available:https://m.eet.com/media/1168696/mixed-signal-soc-verification-using-analog-behavioral-models.pdf
[36]R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed. Norwell: Kluwer Academic Publishers, 2001.
[37]A. Prodic and D. Maksimovic, "Mixed-signal simulation of digitally controlled switching converters," 2002 IEEE Workshop on Computers in Power Electronics, 2002. Proceedings., Mayaguez, Puerto Rico, USA, 2002, pp. 100-105.
[38]Y. Sugimoto, "Sophisticated circuit design and simulation method for switching power converters," 2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Sendai, 2015, pp. 115-117, doi: 10.1109/RFIT.2015.7377905.
[39]Y. Chang, K. Hu, G. Yao, C. Chen and C. Tsai, "Mixed-Level Design Methodology for Digitally Controlled Power Converter IC," 2018 IEEE 7th Global Conference on Consumer Electronics (GCCE), Nara, 2018, pp. 811-812, doi: 10.1109/GCCE.2018.8574849.
[40]張倚華,”應用混層式設計方法之數位控制電源轉換晶片設計,” 國立成功大學電機工程學系碩士論文,2017
[41]J. E. Jang, M. Park and J. Kim, "An event-driven simulation methodology for integrated switching power supplies in SystemVerilog," 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, 2013, pp. 1-7.
[42]S. Liao and M. Horowitz, "A Verilog Piecewise-Linear Analog Behavior Model for Mixed-Signal Validation," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 8, pp. 2229-2235, Aug. 2014, doi: 10.1109/TCSI.2014.2332265.
[43]E. Shera and C. Wegener, "Buck converter modeling in SystemVerilog for verification and virtual test applications," 2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW), Paris, 2015, pp. 1-6.
[44]Kostamovaara, Juha. “MIXED-SIGNAL VERIFICATION OF ANALOG IP USING SCHEMATIC MODEL GENERATOR AND SYSTEMVERILOG.” (2018).
[45]D. Wen, "Analysis of Buck Converter Efficiency," Application Note, AN005, Richtek Technology Corporation, 2014.
[46]K. h. Chen, C. c. Chien, C. h. Hsu, and L. r. Huang, "Optimum power-saving method for power MOSFET width of DC/DC converters," IET Circuits, Devices & Systems, vol. 1, no. 1, pp. 57-62, 2007.
[47]O. Abdel-Rahman, J. A. Abu-Qahouq, L. Huang, and I. Batarseh, "Analysis and Design of Voltage Regulator With Adaptive FET Modulation Scheme and Improved Efficiency," IEEE Transactions on Power Electronics, vol. 23, no. 2, pp. 896-906, 2008.
[48]林詩梅, "具快速響應之電流模式及遲滯定頻降壓型轉換器," 國立成功大學電機工程學系碩士論文, 2014.
[49]C. K. Alexander and M. Sadiku, Fundamental of Electric Circuits, New York:McGraw-Hill, 2004.
[50]A. Prodic, D. Maksimovic, and R. W. Erickson, "Design and implementation of a digital PWM controller for a high-frequency switching DC-DC power converter," in Industrial Electronics Society, 2001. IECON '01. The 27th Annual Conference of the IEEE, 2001, vol. 2, pp. 893-898 vol.2.
[51]S. Cliquennois, A. Donida, P. Malcovati, A. Baschirotto, and A. Nagari, "A 65-nm, 1-A Buck Converter With Multi-Function SAR-ADC-Based CCM/PSK Digital Control Loop," IEEE Journal of Solid-State Circuits, vol. 47, no. 7, pp. 1546-1556, 2012.
[52]A. V. Peterchev, X. Jinwen, and S. R. Sanders, "Architecture and IC implementation of a digital VRM controller," IEEE Transactions on Power Electronics, vol. 18, no. 1, pp. 356-364, 2003.
[53]X. Jinwen, A. V. Peterchev, Z. Jianhui, and S. R. Sanders, "A 4-uA quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications," IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2342-2348, 2004.
[54]陳育煌, "採用堆疊開關功率級之數位降壓晶片設計," 國立成功大學電機工程學系碩士論文, 2016.
[55]A. Prodic and D. Maksimovic, "Design of a digital PID regulator based on look-up tables for control of high-frequency DC-DC converters," in 2002 IEEE Workshop on Computers in Power Electronics, 2002. Proceedings., 2002, pp. 18-22.
[56]A. Hande and S. Kamalasadan, "System modeling and design considerations for point-of-load digital power supplies," in 2008 34th Annual Conference of IEEE Industrial Electronics, 2008, pp. 1004-1009.
[57]C. H. Yang, C. N. Liu, and C. H. Tsai, "Direct digital compensator design for switching converters," in 2010 International Symposium on Next Generation Electronics, 2010, pp. 143-146.
[58]A. V. Peterchev and S. R. Sanders, "Quantization resolution and limit cycling in digitally controlled PWM converters," IEEE Transactions on Power Electronics, vol. 18, no. 1, pp. 301-308, 2003.
[59]A. Syed, E. Ahmed, D. Maksimovic, and E. Alarcon, "Digital pulse width modulator architectures," in 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551), 2004, vol. 6, pp. 4689-4695 Vol.6.
[60]B. J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, "High-frequency digital PWM controller IC for DC-DC converters," IEEE Transactions on Power Electronics, vol. 18, no. 1, pp. 438-446, 2003.
[61]MAXIM.MAX15301. "InTune Automatically Compensated Digital PoL Controller with Driver and PMBus Telemetry" [Online]. Available: http://datasheets.maximintegrated.com/en/ds/MAX15301AA02.pdf
[62]Texas Instruments.TPS65910x "Integrated Power-Management Unit Top Specification"[Online].Available:https://www.ti.com/lit/ds/symlink/tps65910.pdf?ts=1594644235727&ref_url=https%253A%252F%252Fwww.google.com%252F
[63]C. C. Liu, S. J. Chang, G. Y. Huang, Y. Z. Lin, and C. M. Huang, "A 1V 11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18µm CMOS," in 2010 Symposium on VLSI Circuits, 2010, pp. 241-242