| 研究生: |
王瑞汛 Wang, Ruei-Syun |
|---|---|
| 論文名稱: |
主動區間干擾消除演算法之低複雜度設計與實現 Low Complexity Design and Implementation of Active Interference Cancellation |
| 指導教授: |
郭致宏
Kuo, Chih-Hung |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2009 |
| 畢業學年度: | 97 |
| 語文別: | 中文 |
| 論文頁數: | 67 |
| 中文關鍵詞: | 軟硬體共同設計 、偵測與躲避演算法 、主動消除區間干擾 、感知無線電 |
| 外文關鍵詞: | Active interference cancellation, Hardware software co-design, Detection and avoidance., Cognitive radio |
| 相關次數: | 點閱:113 下載:1 |
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本論文提出低複雜主動消除區間干擾演算法之軟硬體架構,且利用軟硬體共同設計的概念,設計整體演算法架構。我們以減少LS estimate運算次數來簡化主動消除區間干擾演算法,並且進一步提出硬體架構。演算法將分為軟硬體兩部份,其中較複雜且無規則性為軟體部分,相反的將具有規則性的部份則為硬體,實現方式軟體部分是以MATLAB實現,硬體方式是以FPGA實現,並且利用Verilink作為FPGA和MATLAB之間溝通的介面,以達到軟硬體共同驗證。利用硬體加速的方式提升整體演算法運算速度。硬體面積僅1039 gates,整體效能可以達到約-40dB的帶拒能力。
The thesis presents hardware/software architecture and implementation of low complexity active interference cancellation. Hardware/software co-design methodology was used to design architecture. We reduce the computational time of LS estimate that to simplify active interference cancellation. We also proposed hardware structure for LS estimate. The algorithm has been separated two parts. The regular part is hardware and the other part is software. The software part was carrier our MATLAB, and hardware was implement by FPGA board. Verilink apply communication interface between FPGA with Matlab, therefore we use Verilink to complete hardware/software co-verification. We used hardware accelerate methodology to promote speed of algorithm. Proposed hardware structure only 1039 gates, which is very low cost. Our architecture have to -40dB notch depth.
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