隨著積體電路設計技術的快速發展，中央處理器單元已經變成低成本元件。8 位元微控制器為早期發展的單晶片系統，直至目前為止仍被廣泛的應用。為了能使8位元微控制器有更好的效能，我們將8位元微控制器管線化。
管線化改進了每個指令的平均執行時間，並且會讓CPI降低和提高時脈速率。但是在管線設計中許多的困難源自於複雜的指令集：指令長度與執行時間的不同可能會造成管線階段間的不平衡，使得hazard偵測和中斷處理的設計複雜化；而複雜的定址模式可能會造成不同的問題，需要多重記憶體存取的定址模式不但大大地使得管線的控制複雜化，而且使管線不能順利執行。另外還有兩個因素會限制管線的效能，第一個因素是control hazards，若增加管線深度，跳躍指令就會變慢，因此會增加程式的執行時間。第二個因素是data hazards，當發生data hazard時，增加管線的深度會增加每個指令的時間，因為指令中許多的週期都會變成暫停。我們為了管線化8位元微控制器，必須克服變動長度指令集和複雜的定址模式。因此，我們設計了Instruction Buffer和Indirect Registers來解決。

Pipelining improves the average execution time per instruction, with offering both a low CPI and a fast clock rate. Many of the difficulties of pipelining arise because of instruction set complications. Variable instruction lengths and running times can lead to imbalance among pipeline stages. They can also severely complicate hazard detection and the maintenance of exceptions. Complex addressing modes can lead to different problems. Multiple memory accesses complicate pipeline control and make it difficult to keep the pipeline flowing smoothly. Two factors combine to limit the performance improvement gained by pipelining. First, control hazards mean that increasing pipeline depth results in slower branch instructions, and increasing the clock cycles for the program. Second, data hazards in the program mean that increasing the pipeline depth increases the time per instruction because a larger percentage of the cycles become stalls. We design the Instruction Buffer and Indirect Registers to resolve the problem due to variable lengths instruction and complex addressing modes.

[1] John L. Hennessy, and David A. Patterson, “Computer Architecture A Quantitative Approach,” 3rd edition.
[2] David A. Patterson, and John L. Hennessy, “Computer Organization & Design The Hardware / Software Interface,” 2nd edition.
[3] Intel Corporation, “MSC51 Microcontroller Family User’s Manual,” 1994.
[4] Curnow, H. J. and B. A. Wichmann, “A synthetic benchmark,” The Computer J. 19(1), 1976.
[5] Weicker, R. P., “Dhrystone: A synthetic systems programming benchmark,” Comm. ACM, 1984.
[6] J. Bayko, “Great Microprocessors of the Past and Present,” 1996.
[7] Patterson, D., “Reduced instruction set computers,” Comm. ACM 28, 1985.
[8] Kane, G., and J. Heinrich, MIPS RISC Architecture, Prentice Hall, Eaglwood Cliffs, NJ, 1992.
[9] McFarling, S. and J. L. Hennessy., “Reducing the cost of branches,” Proc. 13th Symposium on Computer Architecture, Tokyo, 1986.
[10] Smith, J. E. and A. R. Pleszkun, “Implementign precise interrupts in pipelined processors,” IEEE Trans. on Computers, 1988