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研究生： 梁沛基
Leong, Pui-Kei
論文名稱： 數位三角積分脈波寬度調變控制之1MHz直流-直流切換式電源轉換器設計
Design of Sigma-Delta DPWM Controller for 1MHz DC-DC Switch-Mode Power Supplies
指導教授： 蔡建泓
Tsai, Chien-Hung
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2009
畢業學年度： 97
語文別： 英文
論文頁數： 107
中文關鍵詞： 數位三角-積分調變器 、直流-直流切換式電源轉換器 、數位脈波寬度調變器
外文關鍵詞： switch-mode power supplies, DC-DC converter, sigma-delta DPWM
相關次數： 點閱：80  下載：0 
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    • 隨著數位控制器於直流-直流切換式電源轉換器能帶來很多顯著的好處，本論文將提出一個數位三角-積分脈波寬度調變控制之1MHz直流-直流切換式電源轉換器設計，從而達到快速暫態響應以及低功率消耗的優點。
    利用二階多位元數位三角-積分調變器，本論文之控制器只需要一個低功耗、低解析度的數位寬度調變器。因為三角-積分調變可大大提升數位寬度調變器之等效解析度。另外，使用查表法之數位比例積分微分(PID)補償器取代傳統的乘法器架構以節省晶片實現面積。同時，經修正之線性類比至數位轉換器(ADC)能有效降低系統對切換雜訊的影響。最後，本論文將比較Matlab/Simulink模擬結果與FPGA實驗結果來證明系統設計的正確性。

    Based on digital controllers offering significant advantages in Switch-Mode Power Supplies (SMPS), the aim of this work is to develop a sigma-delta DPWM controller for 1MHz DC-DC SMPS to achieve both fast transient response and low power consumption.
    Utilizing a multi-bit digital second order sigma-delta modulator, the proposed controller is only required a low-power low-resolution DPWM since the total effective DPWM resolution is improved by the sigma-delta modulation to avoid limit cycle oscillations (LCOs). In addition, the conventional multiplier based digital PID compensator is replaced by the look-up table based architecture to decrease the area consumption, while the modified linear ADC reduces the influence of switching noise on operation of SMPS. Finally, the Matlab/Simulink simulation and FPGA experimental results are compared to verify the validity of the proposed work.

    Chapter 1 Introduction 1 1.1 Previous Art and Research Motivation 1 1.2 The Challenge of High-Frequency Digital-Control SMPS 3 1.3 Research Goals and Contributions 4 1.4 Thesis Organization 5 Chapter 2 Fundamental of Digitally Controlled DC-DC SMPS 7 2.1 Basic principles of SMPS Buck Converter operation 7 2.1.1 PWM operation 11 2.1.2 Output Filter Design 12 2.1.3 Source of Dissipation 14 2.2 General Digital Controller Architecture 19 2.3 Analog-to-Digital Converter Design Requirement 20 2.3.1 Noise and Temperature Performance 23 2.3.2 Delay-Line Analog-to-Digital Converter for SMPS applications 24 2.4 Digital PID compensator 28 2.4.1 Multiplier based Digital PID Compensator 29 2.4.2 Loop-Up Table Based Digital PID Compensator 30 2.5 Digital Pulse-Width Modulator 31 2.5.1 Resolution Requirement for DPWM 32 2.5.2 Counter-based DPWM 34 2.5.3 Delay-Line based DPWM 35 2.5.4 Hybrid Counter-Delay Line DPWM 36 2.6 Modeling of Uncompensated System Plant, ADC, and DPWM 37 2.7 Sigma-Delta DPWM Controller for a purposed DC-DC SMPS 42 2.7.1 Digital Sigma-Delta PWM Controller for SMPS 42 2.7.2 Low Power ΣΔ DPWM 45 2.8 Summary 47 Chapter 3 High-Frequency ΣΔ DPWM 48 3.1 Digital Pulse-Width Modulators Based on the Noise-Shaping Concept 48 3.2 1st Order ΣΔ Noise Shaping DPWM 50 3.3 Output Voltage Tones generated by the 1st Order ΣΔ modulator 54 3.4 Attenuation of Low-Frequency Tones and Fast Convergence by the 2nd Order ΣΔ modulator 59 3.5 Dynamic Model for 2nd Order ΣΔ DPWM 66 3.6 Effective ΣΔ DPWM Resolution 67 3.7 Circuit Implementation 68 3.8 Summary 70 Chapter 4 ADC Encoder and Compensator 71 4.1 Analog to Digital Encoder 71 4.2 Loop-Up Table Based Digital PID compensator 72 4.2.1 Design of Digital PID compensator 73 4.2.2 Implementation of Loop-Up Table Based Digital PID compensator 77 4.3 Summary 79 Chapter 5 Simulation Results 80 5.1 The Simulation Models 80 5.2 Open-Loop System Verification for DPWM Resolution and Linearity Test 80 5.3 Close-Loop System Verification for DC-DC SMPS 82 5.4 Summary 86 Chapter 6 FPGA Experimental Results 87 6.1 FPGA Experimental Hardware Setup 87 6.2 DPWM Resolution and Linearity Test Results 88 6.3 Digital Controller Closed Loop Response 91 6.3.1 Steady-State Response 92 6.3.2 Load Transient Response 94 6.4 Summary 97 Chapter 7 Conclusions and Future Work 98 7.1 Future Work 98 Reference 100 Appendix 104

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