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研究生：	蕭珮珊 Hsiao, Pei-Shan
論文名稱：	支援作業系統執行且具備前端與記憶體子系統優化之六級RV64IMA模組化CPU實作 Implementation of an OS-compatible 6-stage RV64IMA Modular CPU with Frontend and Memory Optimizations
指導教授：	陳中和 Chen, Chung-Ho
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2026
畢業學年度：	114
語文別：	中文
論文頁數：	99
中文關鍵詞：	RISC-V 、作業系統相容處理器、RV64IMA 、Linux 、記憶體子系統
外文關鍵詞：	RISC-V, OS-compatible processor, RV64IMA, Linux, memory subsystem
相關次數：	點閱：63 下載：0
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隨著嵌入式系統與邊緣運算應用日益複雜，處理器平台已不再僅需執行bare-metal 程式，也必須支援即時作業系統與通用作業系統。對RISC-V處理器而言，作業系統相容性不僅包含基本指令集正確性，也涉及特權模式、例外與中斷處理、原子操作、虛擬記憶體、計時器中斷與基本SoC周邊等系統機制。本論文提出並實作一個可支援作業系統執行的六級RV64IMA模組化CPU，稱為Lunacore，目標是在維持 in-order execution 與 in-order commit 之硬體複雜度與可驗證性的同時，建立可啟動 FreeRTOS 與 Linux 的RISC-V 處理器平台。
在微架構設計方面，Luna採用六級single-issuein-order pipeline，並透過明確的提交流程支援precise exception、CSR 存取與特權模式執行。為改善指令供應，本研究設計decoupled frontend，將 next-PC generation、branch prediction 與 instruction fetch 解耦，降低branchredirect 與取指延遲對管線的影響。在記憶體子系統方面，Luna整合 pipelined VIPT L1 cache、Sv39 MMU、ITLB/DTLB、page table walker、store-to-load forwarding 與 atomic memory operation 支援，使核心能處理 Linux 所需的位址轉譯、 page fault、同步操作與特權模式下的記憶體存取行為。本研究亦建立SoC模擬平台，整合CLINT、PLIC、UART、AXI-basedinterconnect與主記憶體模型，完成處理器核心、系統周邊與Linux軟體環境之整合。
為驗證設計正確性，本研究建立多層次validationinfrastructure，包含RISC-V指令測試、LunaISS、commit-level co-simulation、Konata pipeline viewer 與 fast Linux booting mode。實驗結果顯示，Luna可通過RV64IMA指令層級測試，成功執行FreeRTOS，並可啟動Linux kernel v5.15，完成由 M-mode OpenSBI、S-mode Linux kernel 到 U mode console 的完整開機流程。此結果證明Luna具備支援實際作業系統所需之特權模式切換、中斷、計時器、MMU、UARTconsole與使用者空間執行能力。
效能評估方面，本研究以CVA6作為主要in-orderbaseline，並使用CoreMark、Dhry stone、MiBench、PolyBench 與 EmBench 分析不同 workload 下的表現。結果顯示， Luna 在 CoreMark/MHz 與 Dhrystone 中相較 CVA6 分別提升約 5.1% 與 7.3%，在 MiBench 與 PolyBench 中分別達到 1.107× 與 1.065× 的 geometric mean speedup，整體benchmark 類型之overall geometric mean speedup 為 1.063×。此外，Luna 於 16nm FinFET 製程下可達到1GHz 目標頻率，合成後總cellarea 為363,438.1µm2，post synthesis average power estimate 為 197.8mW。綜合而言，本論文完成一個具備作業系統相容性的RV64IMAin-order CPU 與 SoC 平台，可作為後續RISC-VOS-capable processor 與 Linux workload 分析之研究基礎。

This thesis presents Luna core, an OS-compatible six-stage RV64IMA modular CPU and SoC simulation platform. The work targets a RISC-V processor capable of exe-cuting FreeRTOS and Linux while retaining the simplicity and verifiability of in-order execution and in-order commit. Luna integrates a decoupled frontend, a pipelined VIPT L1 cache, Sv39 virtual memory support, TLBs, a page table walker, store-to-load for-warding, atomic memory operations, and basic SoC peripherals including CLINT, PLIC, UART, an AXI-based interconnect, and main memory. A multi-level validation infras-tructure, including RISC-V instruction tests, LunaISS, commit-level co-simulation, a Konata pipeline viewer, and a fast Linux booting mode, is used to verify functionality and support long-running system workloads. Experimental results show that Luna passes RV64IMA instruction-level tests, executes FreeRTOS, and boots Linux kernel v5.15 from OpenSBI to a user-mode console. Compared with CVA6, Luna improves Core-Mark/MHz and Dhrystone by about 5.1% and 7.3%, achieves geometric mean speedups of 1.107×on MiBench and 1.065×on PolyBench, and obtains an overall speedup of 1.063×across benchmark categories. Post-synthesis evaluation in a 16nm FinFET process shows that Luna reaches 1GHz with a cell area of 363,438.1μm2 and an average power estimate of 197.8mW.

摘要 i
英文延伸摘要 ii
誌謝 vii
目錄 viii
表格 xi
圖片 xii
Chapter 1. Introduction 1
1. Motivation 1
2. Thesis Contributions 2
3. Thesis Organization 2
Chapter 2. Background 3
1. CPU Fundamentals 3
1.1. Instruction Flow and Pipeline Abstraction 3
1.2. ISA vs. Microarchitecture 4
1.3. Basic Performance Considerations 4
2. Operating System Fundamentals 5
2.1. The Role and Functions of an Operating System 5
2.2. Overview of Target Operating Systems 5
FreeRTOS 5
Linux6
2.3. The Necessity of OS Compatibility 6
3. Virtual Memory Fundamentals 7
3.1. Motivation and Benefits 7
3.2. Address Translation, TLB, PTW, and Page Fault Handling 7
3.3. RISC-V Virtual Memory Overview 8
4. RISC-V ISA and System Architecture Requirements 8
4.1. Overview and Advantages of RISC-V 8
4.2. Base ISA and Required Extensions 9
4.3. Privilege Levels for OS Execution 10
4.4. Essential SoC Units for Operating Systems 10
4.5. System Architecture 11
AXI-based SoC Interconnect 11
Compute Subsystem Overview 12
OS-critical Peripherals 12
Memory Configuration in Current Prototype 12
Chapter 3. Microarchitectural Implementation of the Core Pipeline 14
1. Overview of the 6-stage Pipeline 14
1.1. Role of ROB and RAT in the In-order Pipeline 17
2. Decoupled Frontend Design 18
2.1. Branch Prediction Unit 19
3. Pipeline Control and Hazard Management 20
3.1. Prediction Flow 20
3.2. Redirect Mechanism 21
3.3. Data Hazard Management 21
3.4. Exception Handling 22
Chapter 4. Memory Subsystem Design 24
1. Memory Subsystem Overview 24
2. Load/Store Unit Design 26
3. Pipelined VIPT L1 Cache and Sv39 MMU 28
3.1. VIPT L1 Cache Organization 29
3.2. Overlapped TLB Lookup and Cache Meta Access 30
3.3. Store Address Translation Reuse 30
3.4. Sv39 MMU and Page Table Walk Integration 32
4. Atomic Instruction Support in the Cache Subsystem 33
5. Memory Access Flow 35
6. Design Summary 36
Chapter 5. Linux Bring-up and Software Environment 37
1. Overview of the Software Development Environment 37
2. The RISC-V Booting Sequence 37
2.1. OpenSBI 38
2.2. Linux Kernel 39
2.3. Init Process 40
3. Build and Integration Pipeline 40
3.1. Toolchain Selection 41
3.2. Device Tree Description and Hardware Integration 41
3.3. Linux Kernel Build Configuration 42
3.4. OpenSBI Integration with fw_payload 42
3.5. Root File System Construction and Initial RAM Disk Integration 43
3.6. Linux Boot Flow in the Verilator-based SoC Simulation 44
3.7. Build Automation and Reproducibility 45
4. Summary 45
Chapter 6. Validation Methodology and Infrastructure 47
1. Instruction Set Simulator 47
2. RTL Simulation Environment and Co-Simulation Framework 48
3. Pipeline Viewer: Konata 50
3.1. Konata Overview 50
3.2. Integration with the Simulation Flow 51
3.3. Implementation Details 52
4. Linux Booting and Fast Booting Mode 53
5. Summary 56
Chapter 7. Experimental Results and Evaluation 57
1. Validation 57
1.1. Instruction-level Validation 58
1.2. Operating System Validation 58
2. Implementation Analysis 60
2.1. Linux Cache Configuration Analysis 60
2.2. Post-synthesis Result 62
2.3. Power Breakdown 63
2.4. Hardware Design Comparison with CVA6 64
3. Evaluation 65
3.1. Evaluation Configuration 66
3.2. CoreMark and Dhrystone 67
3.3. MiBench 69
3.4. PolyBench 72
3.5. EmBench 75
3.6. Overall Performance Summary 77
4. Summary 80
Chapter 8. Conclusion 81
1. Future Work 83
References 84
                                    

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[7]R.-V. International and W. D. Corporation, “Opensbi (risc-v open source supervisor binary interface),” 2019-2026, accessed: [Insert Date Here]. [Online]. Available: https://github.com/riscv-software-src/opensbi
[8]R.-V. International, “Risc-v advanced core local interruptor (aclint) specification,” 2025, accessed: 2026-05-11. [Online]. Available: https://github.com/riscv/riscv-aclint
[9]A. Waterman, K. Asanović, and J. Hauser, “The RISC-V Instruction Set Manual, Vol ume II: Privileged Architecture, Document Version 20211203,” RISC-V International, San Francisco, Tech. Rep., dec 2021. [Online]. Available: https://riscv.org
[10]Y.-T. Zhuang, P.-S. Hsiao, and C.-H. Chen, “Lunaiss: A risc-v simulator for branch pre dictor validation and interval-based profiling,” in 2025 22nd International SoC Design Conference (ISOCC). IEEE, 2025, pp. 1–2.
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