本論文提出應用於具低ESR電容之低壓降調節器的由上至下設計方法，結合系統行為建模、系統層級設計與電路優化技術於一完整流程。
首先，系統行為模型採納Verilog-A類比硬體描述語言與電晶體元件模型結合成一混合層級系統模型，提供了具低ESR電容低壓降調節器之重要特性的正確行為建模。第二，應用所提出之混合層級模型，透過提出之系統層級設計流程可將系統效能參數分離，幫助設計者權衡設計考量，減少設計反覆的發生。第三，應用於低壓降調節器中誤差放大器設計的gm/ID技術將被提出，在達成目標規格的同時減少電流消耗。
所提出之設計方法將應用在輸入電壓3.3V、輸出電壓2.8V以及最大輸出電流100mA之設計範例，系統穩定性在0mΩ至30mΩ的電容ESR範圍得到確保。此外，由於導通元件設計對於低壓降調節器相當重要，本論文亦探討飽和區與線性區的導通元件設計之差異，因此針對同一目標規格的兩個設計範例將被實作與驗證。模擬結果顯示所提出之設計方法能有效實現規格導向的流程，除了加速開發與除錯，並且調節器效能得到優化。

This thesis proposes a top-down design methodology applied to low-dropout regulators with low ESR capacitance. It includes system behavioral modeling, system-level design and circuit optimization technique in a complete flow.
Firstly, the system behavioral model adopts Verilog-A, an analog hardware description language, and the transistor device model together to create a mixed-level system model, providing correct modeling capabilities of important characteristics of low-dropout regulators with low ESR capacitance. Secondly, with the proposed mixed-level model, the proposed system-level design flow separates the performance parameters of the system. This helps designers consider the design trade off and reduce design iterations. Thirdly, the gm/ID technique which is applied to error amplifier design in low-dropout regulator is proposed to reduce current consumption while achieving objective specifications simultaneously.
The proposed methodology was applied to the design case of low-dropout regulator with supply voltage of 3.3V, output voltage of 2.8V and maximum load current of 100mA and the system stability in the capacitance ESR range between 0mΩ and 30mΩ was guaranteed. Moreover, due to the importance of the pass element design to low-dropout regulators, this thesis also discusses the difference between the saturation region approach and the linear region approach of pass element design, so both approaches were implemented and verified due to the same target specifications. Simulation results reveal that the proposed methodology realized specification-oriented flow which not only speeds development and debugging but also optimizes the performance of the regulator.

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