本論文主要是研究高效益節能非揮發性微處理器，利用非揮發性記憶體在無電源情況下依然可維持資料的特性，相較一般微處理器有助於降低系統待機能耗。在此提出兩大電路:非揮發性感測匯流器、非揮發性微處理器。在電路內皆嵌入非揮發性電阻式記憶體，為建置低能耗非揮發性微處理器，研究出各項低能耗非揮發性混合式電路，如非揮發性正反器、非揮發性靜態隨機存取記憶體、非揮發性內容可定址記憶體；以及控制電路的相關低能耗系統設計，如非揮發性記憶體控制器、非揮發性正反器控制器。
研究的低功耗微控制器內嵌電阻式記憶體可應用於物聯網感測匯流器，主要提出微控制器架構中，以嵌入電阻式記憶體作為資料緩衝器。該電阻式記憶體具有抗製程變異之讀取感測放大器，微控制器可依具位元錯誤率調整感測放大器之參考電流放大倍率，相較於傳統感測放大器可降低32%讀取位元錯誤率；若包含記憶體控制器的自我修補電路與BCH錯誤位元校正碼可提升電阻式記憶體良率至100%。另在系統模擬方式比較其他四種新興非揮發性記憶體作為資料緩衝器在系統運算速度與功耗上的差異。現已完成8位元8051微控制器內嵌256 Kb電阻式記憶體晶片，該方法實現於TSMC 0.18 μm CMOS前段製程與工研院電阻式記憶體後段製程。
另一成果，實現具常閉瞬開運算技術之低能耗非揮發性微處理器，以16位元MSP430為基礎架構，內嵌電阻式記憶體、低資料備存能耗非揮發性正反器、非揮發性靜態隨機存取記憶體，以及非揮發性正反器控制器。若用90 nm製程模擬，比較過往的非揮發性微處理器，提出的電路與系統可降低資料備存/回復的時間與能耗並節省面積，且有效提升使用年限與資料回復穩定性。

The nonvolatile memory (NVM) can maintain data in power-off state to reduce system idle energy consumption. This work proposes two new breeds of microprocessors with embedded resistive random-access memories (ReRAMs) from the circuit to the system levels: a nonvolatile (NV) sensor hub and a NV microprocessor (NV-μP). To build a low energy NV-μP, the low energy NV hybrid circuits are designed and developed such as NV flip-flop (NV-FF), NV static random access memory, and NV content-address memory. At the system level, the NV circuit controllers including the NVM and NV-FF to achieve low energy designs.
The proposed low power microcontroller unit (MCU) with embedded ReRAM can apply to a sensor hub, as in a precomputation system of Internet-of-Things. This idea is to make the embedded ReRAM as a data buffer. The ReRAM was equipped with a novel sense amplifier that had three magnification times for the reference cell current, to increase the read yield by 32%. Furthermore, the ReRAM controller included built-in self-repair and a shortened Bose–Chaudhuri–Hocquenghem (99, 64, 5) error-correlating code can yield ReRAM up to approximately 100%. The embedded ReRAM architecture was compared with the other four types of NVMs in system speed and power consumption. An 8-bit 8051 MCU with an embedded 256Kb ReRAM was thus implemented to verify the concept. The chip was manufactured using 0.18 μm CMOS front-end-of-line (FEOL) process and Industrial Technology Research Institute (ITRI) ReRAM back-end-of-line (BEOL) process.
The other study proposes a low energy NV-μP using normally-off computing technology. It is based on a 16-bit MSP430-compatilbe architecture with an embedded ReRAM, low store energy NV-FFs, a NV-SRAM, and a NV-FF controller. Then the proposed design when compared with prior NV-μPs can reduce store/restore time, energy consumption, and area overhead for simulations using 90 nm technology. Besides, the proposed system mechanisms increase lifetime and data recovery stability.

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