近年人工智慧與大量資料平行運算的需求持續提升 GPU 的重要性，這類處理器採用 Single Instruction, Multiple Threads (SIMT) 程式模型。RISC-V 因其開放且模組化的指令集架構，成為探索 GPGPU 設計的良好基礎；然而在架構探索過程中，compiler、driver、runtime 與應用程式皆需要一個能完全實現 guest 指令集且執行快速的模擬器。傳統直譯式指令集模擬器雖易於實作，但指令解碼、architectural state 存取與排程開銷會成為主要瓶頸；既有二進制翻譯技術則多以彼此獨立的 MIMD core 為前提，難以直接對應 SIMT 的 warp lockstep execution、branch divergence 與 block-scoped synchronization。

本論文提出 GPUSim，一個以 ahead-of-time (AOT) static binary translation 為核心的 RISC-V SIMT 模擬器。GPUSim 先將 RISC-V SIMT ELF 轉換為 LLVM IR，再 lower 成 host platform 可直接執行的原生程式碼，並以 simulation runtime 管理 kernel 派發、記憶體物件與 guest architectural state，使 OpenCL 與 OpenGL 能共用同一套介面。GPUSim 提供兩種互補的執行後端：CPU backend 將 guest thread block 分配至多個 host worker thread，並在每個 worker thread 內以 SIMD 指令執行 warp lane，透過 active mask、block chaining 與 static single assignment (SSA) forwarding 保留 branch divergence、predicated execution 與 architectural register 更新的語意；GPU backend 則採用 SIMT-on-SIMT 對應方式，將 guest thread 與 thread block 直接映射至 host GPU 的 thread 與 thread block，重用原生 GPU 的 warp scheduling、branch divergence 處理與 block-wide synchronization。對於 OpenGL graphics pipeline，GPUSim 進一步將 primitive binning、rasterization、tile load/store 與 render output 等固定功能階段以 CUDA kernel 實作，使 compute 與 graphics workload 能在同一框架中執行。

本論文以 microbenchmark、Rodinia OpenCL benchmark、Gemma3-1B inference 與多組 OpenGL graphics workload 評估 GPUSim。實驗顯示，AOT translation、host multithreading 與 SIMD execution 能對直譯式 baseline 帶來顯著加速，而 GPU backend 在規則且高度平行的 workload 上速度最快；在 Gemma3-1B inference 上，GPU backend 僅比原生 GPU 執行慢約 50%。這些結果顯示 GPUSim 能在維持 SIMT 執行語意的同時，有效利用 host platform 的平行硬體資源，並透過 tracing 機制支援 workload 行為分析，可作為 RISC-V SIMT 指令集架構、compiler 與 GPU runtime 設計的平台。

The growing demand for artificial intelligence and massively data-parallel computation has made GPUs increasingly important, and such processors commonly adopt the Single Instruction, Multiple Threads (SIMT) programming model. With its open and modular instruction set architecture, RISC-V provides a solid foundation for exploring GPGPU designs. Throughout such architectural exploration, however, the compiler, driver, runtime, and applications all require a simulator that faithfully realizes the guest instruction set while running fast. Traditional interpretive instruction set simulators are easy to implement, but instruction decoding, architectural state access, and scheduling overhead become the main bottlenecks. Existing binary translation techniques, in turn, typically assume mutually independent MIMD cores and thus map poorly onto SIMT warp lockstep execution, branch divergence, and blockscoped synchronization.

This thesis presents GPUSim, a RISC-V SIMT simulator built around ahead-of-time (AOT) static binary translation. GPUSim first translates a RISC-V SIMT ELF into LLVM IR and then lowers it into native code that runs directly on the host platform. A simulation runtime manages kernel dispatch, memory objects, and guest architectural state, allowing OpenCL and OpenGL to share the same interface. GPUSim provides two complementary execution backends. The CPU backend distributes guest thread blocks across multiple host worker threads and executes warp lanes with SIMD instructions within each worker thread, preserving the semantics of branch divergence, predicated execution, and architectural register updates through active masks, block chaining, and static single assignment (SSA) forwarding. The GPU backend adopts a SIMT-on-SIMT mapping that directly maps guest threads and thread blocks onto host GPU threads and thread blocks, reusing the native GPU’s warp scheduling, branch divergence handling, and intra-block synchronization. For the OpenGL graphics pipeline, GPUSim further implements fixed-function stages such as primitive binning, rasterization, tile load/store, and render output as CUDA kernels, so that compute and graphics workloads can run within the same framework.

This thesis evaluates GPUSim with microbenchmarks, the Rodinia OpenCL benchmark, Gemma3-1B inference, and several OpenGL graphics workloads. The experiments show that AOT translation, host multithreading, and SIMD execution deliver substantial speedups over an interpretive baseline, while the GPU backend is fastest on regular, highly parallel workloads; on Gemma3-1B inference, the GPU backend is only about 50% slower than native GPU execution. These results demonstrate that GPUSim can effectively exploit the host platform’s parallel hardware while preserving SIMT execution semantics, and that its tracing mechanism supports workload behavior analysis, making it a viable platform for the design of RISC-V SIMT instruction set architectures, compilers, and GPU runtimes.

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