在電路設計的流程中，行為模型(behavior model)的建立是非常重要的一個環節，藉由比較簡單的高階表示方式與圖形介面，可以讓我們在短時間內針對自己設計的系統進行行為模擬，藉以驗證該設計的正確性。經過行為模型驗證無誤後，再進行電路的設計，能避免直接進入電路設計卻在半途發現有系統考量上的疏失，而要重新設計的風險。
在現有論文中，大多是單就行為模型的建立或是僅著重於delta sigma調變器的電路實現，並沒有將行為模型的平台融入設計流程中，而本篇論文針對這樣的情形提出一套由上至下(top-down)設計流程透過Simulink、Verilog-A兩種模擬方式來輔助delta sigma調變器的設計。
本論文所使用的行為模擬平台分別建置在SIMULINK以及Cadence’s Spectre兩種環境下。最後我們將此設計流程實際套用在一個應用於WCDMA系統中的連續時間帶通delta-sigma調變器的設計上，其規格為中心頻率100MHz，電路內部的量化器(quantizer)操作在400MHz的頻率，此調變器使用TSMC 0.35μm CMOS 製程技術進行模擬，供應電壓為3.3V時，在3.84MHz的頻寬內，最大的SNR可以達到38.6dB，其相對應大約為6-bit的解析度。

In the design flow of circuits, building the behavior models is very important. The behavior of the system can be simulated and the result can be verified in a short time by using a higher level platform and the simpler user interface. Designing the circuit after confirming the simulation results of a behavior model helps the designers avoid making too many mistakes.
From the searched literatures for the design of CT BP delta-sigma modulator, we found that some of them only focused on building a behavior model and others focused only on the circuit implementation. Almost none was found to consider both the behavior model and the physical implementation at the same time. Hence, we develop a top-down design flow using Simulink and Verilog-A for it to facilitate the design work.
This paper presents a design methodology of a continuous-time(CT) Band-pass(BP) delta-sigma modulator which can simplify the design procedure. The models were built in SIMULINK and Cadence’ s Spectre environment. Finally, the flow is used in the design of a CT BP delta-sigma modulator which is applied to a WCDMA communication system. The center frequency of this modulator is at 100MHz and the internal quantizer operated at 400MHz clock frequency. The modulator is simulated in TSMC 0.35μm CMOS technology, at a supply voltage of 3.3V. The maximum SNR is 38.6dB for a 3.84MHz bandwidth, which corresponds to a resolution of 6 bits.

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