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研究生： 蕭國樹
Hsiao, Kuo-Su
論文名稱： 高效能超純量處理器中指令激發單元的最佳化與取捨
Wakeup Logic Optimizations and Trade-off in High-performance Superscalar Processors
指導教授： 陳中和
Chen, Chung-Ho
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2006
畢業學年度： 94
語文別： 英文
論文頁數： 85
中文關鍵詞： 指令激發單元 、超純量處理器
外文關鍵詞： wakeup logic, superscalar
相關次數： 點閱：201  下載：2 
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    • 在高效能的超純量處理器中，由於複雜的指令激發動作，使得動態指令排程器變的更為複雜且愈加沒有擴展性。為了改進動態指令排程器的能量消耗、激發延遲、硬體成本以及擴展性，在本篇論文中我們提出了三種激發單元的最佳化。首先第一種方法是將來源標籤預先解碼，然後只將來源標籤直接與選中的回應訊號比對，如此可將目的標籤的讀取及多餘的比較從指令激發動作中移除。接著，第二種方法則是利用指令激發動作的區域性來將激發動作限制在小區段裡面，以達到降低負載電容及電路活動量的效果。第三種方法以激發位址來將指令重新排序，在指令佇列窗口中將指令依激發位址排列。在指令激發程序中，指令激發的動作只有在被目的標籤的激發位址選中的區段中才會運作。實驗結果顯示出三種提出的最佳化方案可以有效的節省功率消耗、降低激發延遲。另外從實驗結果也可以看出我們所提出的方案具有很好的擴展性。

    In a high-performance superscalar processor, the dynamic instruction scheduler often comes with poor scalability and high complexity due to the expensive instruction wakeup operation. This thesis presents three optimizations for wakeup logic to improve the power consumption, wakeup latency, area cost, and scalability. First, a wakeup design that pre-decodes the source tag is proposed. This design removes the reads of the destination tag and eliminates the redundant tag matches by matching the source tag directly with only the selected grant line. Next, the second design exploits the wakeup locality that most of the wakeup distances between two dependent instructions are short. By limiting the wakeup operation within a small wakeup range, the load capacitance and circuit activities can be alleviated. Third, a scheduling technique is proposed to schedule instructions into the segmented issue window based on their wakeup addresses. During wakeup process, the wakeup operation is only performed in the segment selected by the wakeup address of the result tag. The experimental results show that the proposed designs save the power consumption, and reduce the wakeup latency compared to the conventional designs. The results also show that the proposed designs have excellent scalability.

    摘要 IV ABSTRACT V ACKNOWLEDGMENTS VI CONTENTS VII LIST OF TABLES IX LIST OF FIGURES X CHAPTER 1 INTRODUCTION 1 1.1 POWER BUDGET FOR DESIGNING PROCESSORS 2 1.2 CRITICAL PATH OF PIPELINE STAGES 5 1.3 INSTRUCTIONS PER CYCLE CONSIDERATION 9 1.4 MAIN CONTRIBUTIONS 10 1.5 ORGANIZATION OF THE DISSERTATION 11 CHAPTER 2 BACKGROUND AND METHODOLOGY 12 2.1 SUPERSCALAR PROCESSOR MODELS: AN OVERVIEW 12 2.2 DYNAMIC SCHEDULING 14 2.3 TWO PRIMARY APPROACHES FOR WAKEUP LOGIC 15 2.3.1 CAM-based Approach 15 2.3.2 Gated-off Design 17 2.3.3 Matrix-based Scheme 18 2.4 RELATED WORK 20 2.5 EXPERIMENTAL METHODOLOGY 23 CHAPTER 3 SELECTIVE MATCH DESIGN 26 3.1 MOTIVATION 26 3.2 REDUCING ENERGY AND LATENCY VIA SELECTIVE MATCH 27 3.3 EXPERIMENTAL EVALUATION AND RESULTS 30 3.3.1 Power Consumption 31 3.3.2 Wakeup Latency 33 3.4 SUMMARY 36 CHAPTER 4 WAKEUP LOCALITY DESIGN 37 4.1 WAKEUP LOCALITY IN INSTRUCTION WAKEUP OPERATION 37 4.2 EXPLORING WAKEUP LOCALITY IN CAM-BASED WAKEUP DESIGN 38 4.3 EXPLORING WAKEUP LOCALITY IN MATRIX-BASED WAKEUP DESIGN 44 4.4 EXPLORING WAKEUP LOCALITY IN STP WAKEUP DESIGN 47 4.5 EXPERIMENTAL EVALUATION AND RESULTS 51 4.5.1 Performance 51 4.5.2 Power Consumption 54 4.5.3 Wakeup Latency 57 4.6 SUMMARY 59 CHAPTER 5 WAKEUP ADDRESS SCHEDULING 61 5.1 MOTIVATION 61 5.2 WAKEUP ADDRESS SCHEDULING 61 5.3 EXPERIMENTAL EVALUATION AND RESULTS 64 5.3.1 Performance 64 5.3.2 Power Consumption 66 5.3.3 Wakeup Latency 67 5.4 SUMMARY 69 CHAPTER 6 DISCUSSION AND TRADE-OFF 71 CHAPTER 7 CONCLUSIONS 78 REFERENCES 80 VITA 84 PUBLICATION LIST 85

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