隨著網際網路的廣泛應用，單單具有處理、運算的功能，已經不敷使用，所以本論文研製了一個符合IEEE 802.3 CSMA/CD protocol 乙太網路存取介面的186相容指令之嵌入式單晶片處理器，由於這個單晶片是屬於嵌入式的微處理器，所以乙太網路媒介存取控制晶片，可以傳送直接來自晶片上週邊匯流排欲傳送的資料封包經由MII介面，再傳送到實體層，相反地，則是接受由實體層到MII介面的封包資料，乙太網路存取控制再透過晶片週邊匯流排將資料搬移到系統記憶體中。
在我們的設計中，首先我們先設計一個符合IEEE 802.3標準，同時支援半雙工與全雙工傳送與接收模式的控制晶片，特別是我們在傳送與接收端各配置了二千個位元組的先入先出的記憶體，以為了避免晶片週邊匯流排的頻寬消耗。接著我們將這個乙太網路存取控制晶片整合入一個嵌入式微處理器中，使之成為一個系統單晶片，透過嵌入式微處理器中的直接記憶體存取控制器與中斷控制器，緊緊的整合運作。然後我們以硬體與軟體共同驗證的方式尋找出硬體與軟體的相依性，並將我們的驅動程式載入full HDL system model中，更精確的來驗證我們所製作的系統單晶片。最後經由FPGA demo board，透過實際的網路傳輸線，驗證MAC unit 封包傳送與接收的正確性。

In this thesis, we present a single chip design of a 186 compatible embedded processor with fast Ethernet MAC unit that complies with IEEE 802.3 CSMA/CD protocol. On transmitting, this chip aggregated a valid data frame from the On-chip Peripheral Bus (OPB) to Media Independent Interface (MII) and passed to Physical Layer (PHY). On receiving, the PHY assembled the serial data and passed it to MII. The MAC unit assembled the nibble data into an FIFO and passed it to system memory by the OPB.
We design a MAC unit that supports both full duplex and half duplex mode to transmit and receive frame data. It also supports flow control mode that complies with IEEE 802.3 standard. In order to save OPB bandwidth, we put 2K-byte FIFO into transmit and receive block respectively. Through the DMA controller and interrupt controller of the embedded processor, the MAC unit is incorporated tightly with the processor. Then we look for the dependencies between the hardware and software by hardware/software co-verification model. We put all of our hardware and software designs into a full HDL system model for verification. At last, we use FPGA demo board to transmit and receive frame data through the physical layer chip to verify our design.
The thesis describes the architecture of the processor and media access control protocol of the Ethernet MAC unit. Finally, we show the simulation result and evaluation analysis and implementation result.

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