在本論文中，我們針對不同製程的高壓金氧半場效應電晶體元件的特性以及可靠度進行深入的討論並根據其製程差異解釋電特性及可靠度的物理機制。本篇中所使用的高壓金氧半電晶體主要用於記憶體周邊電路，由於操作電壓相對較高因此元件容易產生熱載子效應，因此我們對在這類型的元件中討論的可靠度會以熱載子為主。
首先在針對高壓元件之應用進行簡單說明，接著介紹在本論文中會用到的可靠度物理機制以及元件製程過程，並且簡介常用於評估元件電性的參數及量測手法，除了量測以外，為了能獲取無法經由量測得到的特性進行更深入的分析，我們用電腦輔助設計(TCAD)元件層級的模擬來進行後續的研究，所以也會簡單說明電腦輔助設計軟體的操作方法。
本論文討論的第一種元件製程差異是改變元件的輕汲極摻雜(Lightly Doped Drain)，首先在不同輕汲極摻雜的元件中我們可以發現，摻雜濃度較高的元件會有較大的汲極電流值，在加較高偏壓後也會有較大的基板電流值，一般而言較大的基板電流值表示元件承受較大的內部電場，並且可靠度熱載子可靠度也會表現較差，但是在本研究中我們發現摻雜濃度較高的元件會有較好的可靠度表現，我們藉由量測的結果以及TCAD模擬元件內部的電場及電流路徑來進一步討論造成這樣不尋常狀況的原因。
本文中第二種元件製程的差異為改變矽凹陷(Si recess)深度的元件間的比較，在本研究中我們發現改變矽凹陷深度的元件電特性的部分沒有明顯的差異，但是在可靠度的部分矽凹陷較深的元件會有較小的基板電流但可靠度表現卻較差，我們藉由模擬結果搭配實際量測值分析元件來解釋會造成他們特性不同的原因。接著我們討論漸進接面元件與傳統接面元件的崩潰電壓效應以及可靠度，對於高壓元件而言，承受較高的電場除了會造成熱載子效應之外，也更容易導致元件崩潰，因此高壓元件的崩潰電壓也常常是一個評估高壓元件特性的指標，對於漸進接面元件而言，我們發現這樣的結構有助於改善元件的崩潰電壓並且不會犧牲元件的基本電性及可靠度。
最後我們針對不同位置縮短元件尺寸來做討論，我們發現在尺寸縮短的過程中元件的基本電性會比較好，然而可靠度也變得比較差，因此我們針對這樣的結果分析最適合微縮元件的位置。

In this thesis, the electric characteristics and reliability of high voltage Metal-Oxide-Semiconductor field effect transistors (HV-MOSFET) with different process are discussed. Base on the process difference and measurement data. The underlying mechanism of the electric parameter and reliability on these devices were fully discussed.
The HV-MOSFET used in this thesis is applied in the periphery circuit of NAND Flash Cell. The operating voltage of this device is relatively high and prone to suffer hot-carrier effect. Thus, the reliability issue would mainly focus on hot-carrier reliability.
The effect of process variation on device parameter and reliability are studied in this thesis. In the front of the thesis, we briefly introduce the structure of the devices used in the following part. The mechanism of hot-carrier effect and process flow will be presented. The electric parameter used to evaluate the device performance and measurement metrology will also be introduced. In addition, the Technology Computer-Aided Design (TCAD) simulation is also performed to evaluate the parameter which could not gain from measurement. Thus, the basic operation of TCAD simulation would be introduced.
The first process variation discussed is the different doping concentration on lightly doped drain (LDD). Firstly, higher drain current is observed on device with higher doping concentration. After higher bias voltage performed on drain side, the higher substrate current is also found on the with higher doping concentration. Generally, higher substrate current indicate that the device suffers higher electric field and usually leading to poor performance on reliability. However, we found that the device with higher doping concentration possess better reliability even though the device suffers higher substrate current. Base on the measurement data and TCAD simulation, the unexpected results are well discussed.
The second process variation discussed is the Si recess depth different. In this study, the electric parameter of device with different recess depth shows no obvious different in HV-MOSFET. But the smaller substrate current is observed on device with deeper recess depth. However, the reliability of device with deeper recess depth is poor than device with shallow recess depth. Such an effect is analyzed base on the measurement data and TCAD simulation. After that, the effect of gradual junction structure on breakdown voltage and reliability are investigated. High electric field lead to not only hot-carrier effect, but also the prone to induce device breakdown. Thus, the breakdown voltage is usually regarded as an index to evaluate a high voltage device. We found that the gradual junction structure lead to higher breakdown voltage but keeps the almost same drain and lifetime. Finally, the shrink of device size on different positions are discussed. Base on the electric parameter and reliability analyze, we propose the best position to shrink the device.

chapter 1 references
[1] S. Manzini and C. Contiero, "Hot-electron-induced degradation in high-voltage submicron DMOS transistors," in 8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings, 1996, pp. 65-68.
[2] A. W. Ludikhuize, M. Slotboom, A. Nezar, N. Nowlin, and R. Brock, "Analysis of hot-carrier-induced degradation and snapback in submicron 50 V lateral MOS transistors," in Proceedings of 9th International Symposium on Power Semiconductor Devices and IC's, 1997, pp. 53-56.
[3] R. Versari, A. Pieracci, S. Manzini, C. Contiero, and B. Ricco, "Hot-carrier reliability in submicrometer LDMOS transistors," in International Electron Devices Meeting. IEDM Technical Digest, 1997, pp. 371-374.
[4] R. Versari and A. Pieracci, "Experimental study of hot-carrier effects in LDMOS transistors," IEEE Transactions on Electron Devices, vol. 46, no. 6, pp. 1228-1233, 1999.
[5] S. Manzini and A. Gallerano, "Avalanche injection of hot holes in the gate oxide of LDMOS transistors," Solid-State Electronics, vol. 44, no. 7, pp. 1325-1330, Jul 2000.
[6] P. Moens, G. V. d. bosch, and G. Groeseneken, "Hot-carrier degradation phenomena in lateral and vertical DMOS transistors," IEEE Transactions on Electron Devices, vol. 51, no. 4, pp. 623-628, 2004.
[7] D. Brisbin, P. Lindorfer, and P. Chaparala, "Substrate Current Independent Hot Carrier Degradation in NLDMOS Devices," in 2006 IEEE International Reliability Physics Symposium Proceedings, 2006, pp. 329-333.
[8] K. M. Wu et al., "Anomalous Reduction of Hot-Carrier-Induced On-Resistance Degradation in n-Type DEMOS Transistors," IEEE Transactions on Device and Materials Reliability, vol. 6, no. 3, pp. 371-376, 2006.
[9] J. F. Chen et al., "Characteristics and improvement in hot-carrier reliability of sub-micrometer high-voltage double diffused drain metal-oxide-semiconductor field-effect transistors," Japanese Journal of Applied Physics Part 1-Regular Papers Brief Communications & Review Papers, vol. 46, no. 4B, pp. 2019-2022, Apr 2007.
[10] J. F. Chen et al., "Drift region doping effects on characteristics and reliability of high-voltage n-type metal-oxide-semiconductor transistors," Japanese Journal of Applied Physics, vol. 55, no. 1, Jan 2016, Art. no. 01ad03.
[11] K. Eriguchi et al., "A new framework for performance prediction of advanced MOSFETs with plasma-induced recess structure and latent defect site," in 2008 IEEE International Electron Devices Meeting, 2008, pp. 1-4.
[12] K. Eriguchi, A. Matsuda, Y. Nakakubo, M. Kamei, H. Ohta, and K. Ono, "Effects of Plasma-Induced Si Recess Structure on n-MOSFET Performance Degradation," IEEE Electron Device Letters, vol. 30, no. 7, pp. 712-714, 2009.
[13] K. Eriguchi, Y. Nakakubo, A. Matsuda, M. Kamei, Y. Takao, and K. Ono, "Threshold Voltage Instability Induced by Plasma Process Damage in Advanced Metal-Oxide-Semiconductor Field-Effect Transistors," Japanese Journal of Applied Physics, vol. 49, no. 8, Aug 2010, Art. no. 08jc02.
[14] Home electronics. Available: https://www.pinterest.com/pin/124763852147398987/
[15] Internet of things. Available: https://www.pinterest.com/pin/73183562673794716/
[16] electric car. Available: https://www.pinterest.com/pin/325736985546985038/
[17] Aircraft. Available: https://www.pinterest.com/pin/557390891381761380/
[18] Examples of consumer electronics. Available: https://www.apple.com/tw/
[19] figure of silicon wafer. Available: http://www.porexfiltration.com/applications/tubular-membrane-app/fluoride-reduction/
[20] concept of internet of things Available: http://www.wulianwangiot.com/iotdasai/441.html
[21] L. Yong Qiang, A. T. Salama, M. Seufert, P. Schvan, and M. King, "Design and characterization of submicron BiCMOS compatible high-voltage NMOS and PMOS devices," IEEE Transactions on Electron Devices, vol. 44, no. 2, pp. 331-338, 1997.
[22] B. S. Doyle and K. R. Mistry, "Anomalous hot-carrier behavior for LDD p-channel transistors," IEEE Electron Device Letters, vol. 14, no. 11, pp. 536-538, 1993.
[23] Y. Shi, N. Feilchenfeld, R. Phelps, M. Levy, M. Knaipp, and R. Minixhofer, "Drift design impact on quasi-saturation & HCI for scalable N-LDMOS," in 2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs, 2011, pp. 215-218.
[24] M. Zitouni et al., "A new lateral power MOSFET for smart power ICs: the "LUDMOS concept"," Microelectronics Journal, vol. 30, no. 6, pp. 551-561, Jun 1999.
[25] N. Klein, S. Levin, G. Fleishon, S. Levy, A. Eyal, and S. Shapira, "Device design tradeoffs for 55v ldmos driver embedded in 0.18 micron platform," in 2008 IEEE 25th Convention of Electrical and Electronics Engineers in Israel, 2008, pp. 736-740.
[26] R. Dreesen et al., "A new degradation model and lifetime extrapolation technique for lightly doped drain nMOSFETs under hot-carrier degradation," Microelectronics Reliability, vol. 41, no. 3, pp. 437-443, Mar 2001.
[27] J. F. Chen, C. Yan, Y. Lin, J. Fan, S. Yang, and W. Shih, "Analysis of GIDL-Induced off-State Breakdown in High-Voltage Depletion-Mode nMOSFETs," IEEE Transactions on Electron Devices, vol. 58, no. 6, pp. 1608-1613, 2011.
[28] O. Semenov, A. Pradzynski, and M. Sachdev, "Impact of gate induced drain leakage on overall leakage of submicrometer CMOS VLSI circuits," IEEE Transactions on Semiconductor Manufacturing, vol. 15, no. 1, pp. 9-18, 2002.
[29] J. Chen, T. Y. Chan, I. C. Chen, P. K. Ko, and C. Hu, "Subbreakdown drain leakage current in MOSFET," IEEE Electron Device Letters, vol. 8, no. 11, pp. 515-517, 1987.
[30] S. A. Parke, J. E. Moon, H. C. Wann, P. K. Ko, and C. Hu, "Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model," IEEE Transactions on Electron Devices, vol. 39, no. 7, pp. 1694-1703, 1992.
[31] C. Ja-Hao, W. Shyh-Chyi, and W. Yeong-Her, "DC pulse hot-carrier-stress effects on gate-induced drain leakage current in n-channel MOSFETs," IEEE Transactions on Electron Devices, vol. 48, no. 12, pp. 2746-2753, 2001.
[32] Y. K. Choi, D. Ha, T. J. King, and J. Bokor, "Investigation of gate-induced drain leakage (GIDL) current in thin body devices: Single-gate ultra-thin body, symmetrical double-gate, and asymmetrical double-gate MOSFETs," Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, vol. 42, no. 4B, pp. 2073-2076, Apr 2003.
[33] T. H. Wang, T. E. Chang, L. P. Chiang, C. H. Wang, N. K. Zous, and C. M. Huang, "Investigation of oxide charge trapping and detrapping in a MOSFET by using a GIDL current technique," IEEE Transactions on Electron Devices, vol. 45, no. 7, pp. 1511-1517, Jul 1998.
[34] N. Yang, W. K. Henson, and J. J. Wortman, "A comparative study of gate direct tunneling and drain leakage currents in N-MOSFET's with sub-2-nm gate oxides," IEEE Transactions on Electron Devices, vol. 47, no. 8, pp. 1636-1644, Aug 2000.
[35] C. Ja-Hao, W. Shyh-Chyi, and W. Yeong-Her, "An analytic three-terminal band-to-band tunneling model on GIDL in MOSFET," IEEE Transactions on Electron Devices, vol. 48, no. 7, pp. 1400-1405, 2001.
[36] C. Hu, Modern semiconductor devices for integrated circuits. Prentice Hall Upper Saddle River, NJ, 2010.
[37] K. S. Tian et al., "An investigation on hot-carrier reliability and degradation index in lateral diffused metal-oxide-semiconductor field-effect transistors," Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 2641-2644, Apr 2008.
[38] H. Enichlmair, J. M. Park, S. Carniello, B. Loeffler, R. Minixhofer, and M. Levy, "Hot carrier stress degradation modes in p-type high voltage LDMOS transistors," in 2009 IEEE International Reliability Physics Symposium, 2009, pp. 426-431.
[39] K. Y. Tai, J. Gong, R. Y. Su, F. C. Yang, and C. L. Tsai, "Analysis of Double Hump Substrate Current in NLDMOSFET," in 2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2010, pp. 193-196.
[40] S. Reggiani et al., "Physics-Based Analytical Model for HCS Degradation in STI-LDMOS Transistors," IEEE Transactions on Electron Devices, vol. 58, no. 9, pp. 3072-3080, 2011.
[41] D. J. Wu et al., "Understanding of hot-carrier-injection induced IDLIN kink effect in sub-100nm HV NLDMOS," in 2012 IEEE International Reliability Physics Symposium (IRPS), 2012, pp. 3B.4.1-3B.4.6.
[42] H. Chou, C. Huang, and J. Gong, "Dimension Dependence of Unusual HCI-Induced Degradation on N-Channel High-Voltage DEMOSFET," IEEE Transactions on Electron Devices, vol. 60, no. 5, pp. 1723-1729, 2013.
[43] W. Sun et al., "Hot-Carrier-Induced On-Resistance Degradation of n-Type Lateral DMOS Transistor With Shallow Trench Isolation for High-Side Application," IEEE Transactions on Device and Materials Reliability, vol. 15, no. 3, pp. 458-460, 2015.
[44] K. R. Hofmann, C. Werner, W. Weber, and G. Dorda, "Hot-electron and hole-emission effects in short n-channel MOSFET's," IEEE Transactions on Electron Devices, vol. 32, no. 3, pp. 691-699, 1985.
[45] J. E. Chung, M. Jeng, J. E. Moon, P. Ko, and C. Hu, "Performance and reliability design issues for deep-submicrometer MOSFETs," IEEE Transactions on Electron Devices, vol. 38, no. 3, pp. 545-554, 1991.
[46] K. N. Quader, C. C. Li, R. Tu, E. Rosenbaum, P. K. Ko, and H. Chenming, "A bidirectional NMOSFET current reduction model for simulation of hot-carrier-induced circuit degradation," IEEE Transactions on Electron Devices, vol. 40, no. 12, pp. 2245-2254, 1993.
[47] P. M. Lee, T. Garfinkel, P. K. Ko, and H. Chenming, "Simulating the competing effects of P- and N-MOSFET hot-carrier aging in CMOS circuits," IEEE Transactions on Electron Devices, vol. 41, no. 5, pp. 852-853, 1994.
[48] Z. J. Ma et al., "Hot-carrier effects in thin-film fully depleted SOI MOSFET's," IEEE Electron Device Letters, vol. 15, no. 6, pp. 218-220, 1994.
[49] A. Narazaki, J. Maruyama, T. Kayumi, H. Hamachi, J. Moritani, and S. Hine, "A 0.35 /spl mu/m trench gate MOSFET with an ultra low on state resistance and a high destruction immunity during the inductive switching," in 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094), 2000, pp. 377-380.
[50] P. Moens, M. Tack, R. Degraeve, and G. Groeseneken, "A novel hot-hole injection degradation model for lateral nDMOS transistors," in International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), 2001, pp. 39.6.1-39.6.4.
[51] P. Moens, J. Mertens, F. Bauwens, P. Joris, W. D. Ceuninck, and M. Tack, "A Comprehensive Model for Hot Carrier Degradation in LDMOS Transistors," in 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007, pp. 492-497.
[52] J. F. Chen, S. Y. Chen, K. M. Wu, and C. M. Liu, "Investigation of Hot-Carrier-Induced Degradation Mechanisms in p-Type High-Voltage Drain Extended Metal-Oxide-Semiconductor Transistors," Japanese Journal of Applied Physics, vol. 48, no. 4, Apr 2009, Art. no. 04c039.
[53] W. Sun et al., "Investigation on hot-carrier-induced degradation for the n-type lateral DMOS with floating p-top layer," in 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2014, pp. 394-397.
[54] S. Wolf, "Silicon Processing for the VLSI Era, Volume 3–The Submicron MOSFET, 1995," ed: Lattice Press.
[55] A. W. Strong et al., Reliability wearout mechanisms in advanced CMOS technologies. John Wiley & Sons, 2009.
[56] H. Chenming, C. T. Simon, H. Fu-Chieh, K. Ping-Keung, C. Tung-Yi, and K. W. Terrill, "Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement," IEEE Journal of Solid-State Circuits, vol. 20, no. 1, pp. 295-305, 1985.

chapter 2 references
[1] Agilent Technologies, B1500A semiconductor device analysis introduction - https://www.testworld.com/used-electronic-test-equipment/keysight-agilent-parametric-test-systems/keysight-agilent-b1500a-semiconductor-device-parameter-analyzer-characterization-system-mainframe-easyexpert/
[2] Agilent Technologies, E5250A low-leakage switch mainframe -https://www.keysight.com/en/pd-116397-pn-E5250A/low-leakage-switch-mainframe?nid=-34003.536883163&cc=US&lc=eng
[3] Swin Super Solution & Service - http://www.3-s.com.tw/fengxi/front/bin/ptdetail.phtml?Part=darkbox_E&Category=64
[4] T. Y. Chan, P. K. Ko, and C. Hu, “A simple method to characterize substrate current in MOSFET's,” IEEE Electron Device Letters, vol. 5, no. 12, pp. 505-507, 1984.
[5] Y. A. El-Mansy, and A. R. Boothroyd, “A simple two-dimensional model for IGFET operation in the saturation region,” IEEE Transactions on Electron Devices, vol. 24, no. 3, pp. 254-262, 1977.
[6] P. K. Ko, R. S. Muller, and C. Hu, "A unified model for hot-electron currents in MOSFET's." In 1981 IEEE International Electron Devices Meeting, 1981, pp. 600-603.
[7] S. Tanaka, and M. Ishikawa, “One-dimensional writing model of n-channel floating gate ionization-injection MOS (FIMOS),” IEEE Transactions on Electron Devices, vol. 28, no. 10, pp. 1190-1197, 1981.
[8] C. Hu, Modern semiconductor devices for integrated circuits: Prentice Hall Upper Saddle River, NJ, 2010.

chapter 3 references
[1] D. Brisbin, P. Lindorfer, and P. Chaparala, "Substrate Current Independent Hot Carrier Degradation in NLDMOS Devices," in 2006 IEEE International Reliability Physics Symposium Proceedings, 2006, pp. 329-333.
[2] K. M. Wu et al., "Anomalous Reduction of Hot-Carrier-Induced On-Resistance Degradation in n-Type DEMOS Transistors," IEEE Transactions on Device and Materials Reliability, vol. 6, no. 3, pp. 371-376, 2006.
[3] J. F. Chen et al., "Characteristics and improvement in hot-carrier reliability of sub-micrometer high-voltage double diffused drain metal-oxide-semiconductor field-effect transistors," Japanese Journal of Applied Physics Part 1-Regular Papers Brief Communications & Review Papers, vol. 46, no. 4B, pp. 2019-2022, Apr 2007.
[4] J. F. Chen et al., "Drift region doping effects on characteristics and reliability of high-voltage n-type metal-oxide-semiconductor transistors," Japanese Journal of Applied Physics, vol. 55, no. 1, Jan 2016, Art. no. 01ad03.
[5] "Hot-electron-induced MOSFET degradation-model, monitor, and improvement," IEEE Trans. Electron Dev., vol. 32, p. 375, 1985.
[6] J. F. Chen, W. Kuo-Ming, L. Kaung-Wan, S. Yan-Kuin, and S. L. Hsu, "Hot-carrier reliability in submicrometer 40V LDMOS transistors with thick gate oxide," in 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual., 2005, pp. 560-564.
[7] K. S. Tian et al., "An investigation on hot-carrier reliability and degradation index in lateral diffused metal-oxide-semiconductor field-effect transistors," Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 2641-2644, Apr 2008.
[8] E. Takeda and N. Suzuki, "An empirical model for device degradation due to hot-carrier injection," IEEE Electron Device Letters, vol. 4, no. 4, pp. 111-113, 1983.
[9] J. Schmidt, F. M. Schuurmans, W. C. Sinke, S. W. Glunz, and A. G. Aberle, "Observation of multiple defect states at silicon silicon nitride interfaces fabricated by low-frequency plasma-enhanced chemical vapor deposition," Applied Physics Letters, vol. 71, no. 2, pp. 252-254, Jul 1997.
[10] W. Tahui, H. Chimoon, P. C. Chou, S. S. Chung, and C. Tse-En, "Effects of hot carrier induced interface state generation in submicron LDD MOSFET's," IEEE Transactions on Electron Devices, vol. 41, no. 9, pp. 1618-1622, 1994.
[11] S. S. Chung and J. Yang, "A new approach for characterizing structure-dependent hot-carrier effects in drain-engineered MOSFET's," IEEE Transactions on Electron Devices, vol. 46, no. 7, pp. 1371-1377, 1999.
[12] A. Tanaka et al., "Quasi-2-Dimensional Compact Resistor Model for the Drift Region in High-Voltage LDMOS Devices," IEEE Transactions on Electron Devices, vol. 58, no. 7, pp. 2072-2080, 2011.

chapter 4 references
[1] K. Eriguchi et al., "A new framework for performance prediction of advanced MOSFETs with plasma-induced recess structure and latent defect site," in 2008 IEEE International Electron Devices Meeting, 2008, pp. 1-4.
[2] K. Eriguchi, A. Matsuda, Y. Nakakubo, M. Kamei, H. Ohta, and K. Ono, "Effects of Plasma-Induced Si Recess Structure on n-MOSFET Performance Degradation," IEEE Electron Device Letters, vol. 30, no. 7, pp. 712-714, 2009.
[3] K. Eriguchi, Y. Nakakubo, A. Matsuda, M. Kamei, Y. Takao, and K. Ono, "Threshold Voltage Instability Induced by Plasma Process Damage in Advanced Metal-Oxide-Semiconductor Field-Effect Transistors," Japanese Journal of Applied Physics, vol. 49, no. 8, Aug 2010, Art. no. 08jc02.
[4] K. Eriguchi and K. Ono, "Impacts of plasma process-induced damage on MOSFET parameter variability and reliability," Microelectronics Reliability, vol. 55, no. 9-10, pp. 1464-1470, Aug-Sep 2015.
[5] H. Chenming, C. T. Simon, H. Fu-Chieh, K. Ping-Keung, C. Tung-Yi, and K. W. Terrill, "Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement," IEEE Journal of Solid-State Circuits, vol. 20, no. 1, pp. 295-305, 1985.
[6] J. F. Chen et al., "Characteristics and improvement in hot-carrier reliability of sub-micrometer high-voltage double diffused drain metal-oxide-semiconductor field-effect transistors," Japanese Journal of Applied Physics Part 1-Regular Papers Brief Communications & Review Papers, vol. 46, no. 4B, pp. 2019-2022, Apr 2007.
[7] E. Takeda and N. Suzuki, "An empirical model for device degradation due to hot-carrier injection," IEEE Electron Device Letters, vol. 4, no. 4, pp. 111-113, 1983.
[8] T. Y. Chan, C. L. Chiang, and H. Gaw, "New insight into hot-electron-induced degradation of n-MOSFETs," in Technical Digest., International Electron Devices Meeting, 1988, pp. 196-199.
[9] K. S. Tian et al., "An investigation on hot-carrier reliability and degradation index in lateral diffused metal-oxide-semiconductor field-effect transistors," Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 2641-2644, Apr 2008.
[10] J. F. Chen, S. Y. Chen, K. M. Wu, and C. M. Liu, "Investigation of Hot-Carrier-Induced Degradation Mechanisms in p-Type High-Voltage Drain Extended Metal-Oxide-Semiconductor Transistors," Japanese Journal of Applied Physics, vol. 48, no. 4, Apr 2009, Art. no. 04c039.
[11] S. Dey, M. Agostinelli, C. Prasad, X. Wang, and L. Shifren, "Effects of Hot Carrier Stress on Reliability of Strained-Si Mosfets," in 2006 IEEE International Reliability Physics Symposium Proceedings, 2006, pp. 461-464.
[12] C. Hyun-Sik, H. Seung-Ho, K. Hee-Sung, and J. Yoon-Ha, "Hot carrier stress in 70-nm nMOSFET with various bias conditions," in 2006 IEEE Nanotechnology Materials and Devices Conference, 2006, vol. 1, pp. 320-321.
[13] J. F. Chen, K. Tian, S. Chen, K. Wu, and C. M. Liu, "On-Resistance Degradation Induced by Hot-Carrier Injection in LDMOS Transistors With STI in the Drift Region," IEEE Electron Device Letters, vol. 29, no. 9, pp. 1071-1073, 2008.
[14] J. F. Chen, K. Tian, S. Chen, K. Wu, and C. M. Liu, "Effect of NDD dosage on hot-carrier reliability in DMOS transistors," in 2009 10th International Symposium on Quality Electronic Design, 2009, pp. 226-229.
[15] H. Yu-Hui et al., "Investigation of monotonous increase in saturation-region drain current during hot carrier stress in N-type Lateral Diffused MOSFET with STI," in 2010 IEEE International Reliability Physics Symposium, 2010, pp. 170-174.
[16] L. Xiao-Yu, T. Brozek, P. Aum, D. Chan, and C. R. Viswanathan, "Degraded CMOS hot carrier life time-role of plasma etching induced charging damage and edge damage," in Proceedings of 1995 IEEE International Reliability Physics Symposium, 1995, pp. 260-265.

chapter 5 references
[1] T. H. Ning, P. W. Cook, R. H. Dennard, C. M. Osburn, S. E. Schuster, and H. Yu, “1 µm MOSFET VLSI technology: Part IV—Hot-electron design constraints,” IEEE Transactions on Electron Devices, vol. 26, no. 4, pp. 346-353, 1979.
[2] K. R. Hofmann, C. Werner, W. Weber, and G. Dorda, “Hot-electron and hole-emission effects in short n-channel MOSFET's,” IEEE Transactions on Electron Devices, vol. 32, no. 3, pp. 691-699, 1985.
[3] M. Yoshida, D. Tohyama, K. Maeguchi, and K. Kanzaki, "Increase of resistance to hot carriers in thin oxide MOSFETS." In 1985 IEEE International Electron Devices Meeting, 1985, pp. 254-257.
[4] T. Tsuchiya, and J. Frey, “Relationship between hot-electrons/Holes and degradation of p- and n-channel MOSFET's,” IEEE Electron Device Letters, vol. 6, no. 1, pp. 8-11, 1985.
[5] R. Versari, and A. Pieracci, “Experimental study of hot-carrier effects in LDMOS transistors,” IEEE Transactions on Electron Devices, vol. 46, no. 6, pp. 1228-1233, 1999.
[6] P. Moens, M. Tack, R. Degraeve, and G. Groeseneken, "A novel hot-hole injection degradation model for lateral nDMOS transistors." In IEEE International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224), 2001, pp. 39-6.
[7] D. Brisbin, A. Strachan, and P. Chaparala, “Optimizing the hot carrier reliability of N-LDMOS transistor arrays,” Microelectronics Reliability, vol. 45, no. 7-8, pp. 1021-1032, Jul-Aug, 2005.
[8] C. C. Cheng, J. F. Lin, T. Wang, T. H. Hsieh, J. T. Tzeng, Y. C. Jong, R. S. Liou, S. C. Pan, and S. L. Hsu, “Physics and Characterization of Various Hot-Carrier Degradation Modes in LDMOS by Using a Three-Region Charge-Pumping Technique,” IEEE Transactions on Device and Materials Reliability, vol. 6, no. 3, pp. 358-363, 2006.
[9] P. Moens, J. Mertens, F. Bauwens, P. Joris, W. D. Ceuninck, and M. Tack, "A Comprehensive Model for Hot Carrier Degradation in LDMOS Transistors." In 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007, pp. 492-497.
[10] K. S. Tian, J. F. Chen, S. Y. Chen, K. M. Wu, J. R. Lee, T. Y. Huang, C. A. Liu, and S. L. Hsu, “An investigation on hot-carrier reliability and degradation index in lateral diffused metal-oxide-semiconductor field-effect transistors,” Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 2641-2644, Apr, 2008.
[11] S. Y. Chen, J. F. Chen, K. M. Wu, J. R. Lee, C. A. Liu, and S. L. Hsu, “Effect of gate voltage on hot-carrier-induced on-resistance degradation in high-voltage n-type lateral diffused metal-oxide-semiconductor transistors,” Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 2645-2649, Apr, 2008.
[12] R. Su, P. Y. Chiang, J. Gong, T. Y. Huang, C. Tsai, C. C. Chou, and C. M. Liu, “Investigation on the Initial Hot-Carrier Injection in P-LDMOS Transistors With Shallow Trench Isolation Structure,” IEEE Transactions on Electron Devices, vol. 55, no. 12, pp. 3569-3574, 2008.
[13] J. F. Chen, S. Y. Chen, K. M. Wu, and C. M. Liu, “Investigation of Hot-Carrier-Induced Degradation Mechanisms in p-Type High-Voltage Drain Extended Metal-Oxide-Semiconductor Transistors,” Japanese Journal of Applied Physics, vol. 48, no. 4, Apr, 2009.
[14] J. F. Chen, K. S. Tian, S. Y. Chen, K. M. Wu, and C. M. Liu, “Mechanism and Modeling of On-Resistance Degradation in n-Type Lateral Diffused Metal-Oxide-Semiconductor Transistors,” Japanese Journal of Applied Physics, vol. 48, no. 4, Apr, 2009.
[15] H. Enichlmair, J. M. Park, S. Carniello, B. Loeffler, R. Minixhofer, and M. Levy, "Hot carrier stress degradation modes in p-type high voltage LDMOS transistors." In 2009 IEEE International Reliability Physics Symposium, 2009, pp. 426-431.
[16] K. Y. Tai, J. Gong, R. Y. Su, F. C. Yang, and C. L. Tsai, "Analysis of Double Hump Substrate Current in NLDMOSFET." In 2010 22nd IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2010, pp. 193-196.
[17] S. Reggiani, S. Poli, M. Denison, E. Gnani, A. Gnudi, G. Baccarani, S. Pendharkar, and R. Wise, “Physics-Based Analytical Model for HCS Degradation in STI-LDMOS Transistors,” IEEE Transactions on Electron Devices, vol. 58, no. 9, pp. 3072-3080, 2011.
[18] S. Poli, S. Reggiani, G. Baccarani, E. Gnani, A. Gnudi, M. Denison, S. Pendharkar, and R. Wise, "Full understanding of hot-carrier-induced degradation in STI-based LDMOS transistors in the impact-ionization operating regime." In 2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs, 2011, pp. 152-155.
[19] D. J. Wu, D. Maji, J. R. Shih, Y. Lee, C. C. Liu, Y. H. Huang, R. Ranjan, and K. Wu, "Understanding of hot-carrier-injection induced IDLIN kink effect in sub-100nm HV NLDMOS." In 2012 IEEE International Reliability Physics Symposium (IRPS), 2012, pp. 3B-4.
[20] H. Chou, C. Huang, and J. Gong, “Dimension Dependence of Unusual HCI-Induced Degradation on N-Channel High-Voltage DEMOSFET,” IEEE Transactions on Electron Devices, vol. 60, no. 5, pp. 1723-1729, 2013.
[21] W. Sun, C. Zhang, S. Liu, W. Su, A. Zhang, S. Wang, S. Ma, and Y. Huang, "Investigation on hot-carrier-induced degradation for the n-type lateral DMOS with floating p-top layer." In 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2014, pp. 394-397.
[22] W. Sun, C. Zhang, S. Liu, L. Shi, W. Su, A. Zhang, S. Wang, and S. Ma, “Hot-Carrier-Induced On-Resistance Degradation of n-Type Lateral DMOS Transistor With Shallow Trench Isolation for High-Side Application,” IEEE Transactions on Device and Materials Reliability, vol. 15, no. 3, pp. 458-460, 2015.
[23] R. Shirota, T. Endoh, M. Momodomi, R. Nakayama, S. Inoue, R. Kirisawa, and F. Masuoka, "An accurate model of subbreakdown due to band-to-band tunneling and its application." In Technical Digest., IEEE International Electron Devices Meeting, 1988, pp. 26-29.
[24] C. Guangjun, S. K. Manhas, E. M. S. Narayanan, M. M. D. Souza, and D. Hinchley, “Comparative study of drift region designs in RF LDMOSFETs,” IEEE Transactions on Electron Devices, vol. 51, no. 8, pp. 1296-1303, 2004.
[25] S. Hardikar, R. Tadikonda, D. W. Green, K. V. Vershinin, and E. M. S. Narayanan, “Realizing high-voltage junction isolated LDMOS transistors with variation in lateral doping,” IEEE Transactions on Electron Devices, vol. 51, no. 12, pp. 2223-2228, 2004.
[26] K. M. Wu, J. F. Chen, Y. K. Su, J. R. Lee, Y. C. Lin, S. L. Hsu, and J. R. Shih, “Anomalous Reduction of Hot-Carrier-Induced On-Resistance Degradation in n-Type DEMOS Transistors,” IEEE Transactions on Device and Materials Reliability, vol. 6, no. 3, pp. 371-376, 2006.
[27] J. F. Chen, K. M. Wu, J. R. Lee, Y. K. Su, H. C. Wang, Y. C. Lin, and S. L. Hsu, “Characteristics and improvement in hot-carrier reliability of sub-micrometer high-voltage double diffused drain metal-oxide-semiconductor field-effect transistors,” Japanese Journal of Applied Physics Part 1-Regular Papers Brief Communications & Review Papers, vol. 46, no. 4B, pp. 2019-2022, Apr, 2007.
[28] J. F. Chen, C. Yan, Y. Lin, J. Fan, S. Yang, and W. Shih, “Analysis of GIDL-Induced off-State Breakdown in High-Voltage Depletion-Mode nMOSFETs,” IEEE Transactions on Electron Devices, vol. 58, no. 6, pp. 1608-1613, 2011.
[29] C. R. Yan, J. F. Chen, C. Y. Lin, H. T. Hsu, Y. J. Liao, M. T. Yang, C. Y. Chen, Y. C. Lin, and H. H. Chen, “Characteristics of Lateral Diffused Metal-Oxide-Semiconductor Transistors with Lightly Doped Drain Implantation through Gradual Screen Oxide,” Japanese Journal of Applied Physics, vol. 52, no. 4, Apr, 2013.
[30] E. Takeda, and N. Suzuki, “An empirical model for device degradation due to hot-carrier injection,” IEEE Electron Device Letters, vol. 4, no. 4, pp. 111-113, 1983.
[31] H. Chenming, C. T. Simon, H. Fu-Chieh, K. Ping-Keung, C. Tung-Yi, and K. W. Terrill, “Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement,” IEEE Journal of Solid-State Circuits, vol. 20, no. 1, pp. 295-305, 1985.
[32] T. Y. Chan, C. L. Chiang, and H. Gaw, "New insight into hot-electron-induced degradation of n-MOSFETs." In IEEE International Electron Devices Meeting, 1988, pp. 196-199.

chapter 6 references
[1] Y. Nishioka, K. Ohyu, Y. Ohji, and T. P. Ma, “Channel length and width dependence of hot-carrier hardness in fluorinated MOSFETs,” IEEE Electron Device Letters, vol. 10, no. 12, pp. 540-542, Dec, 1989.
[2] M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai, “A 40 nm gate length n-MOSFET,” IEEE Transactions on Electron Devices, vol. 42, no. 10, pp. 1822-1830, Oct, 1995.
[3] R. Woltjer, G. M. Paulzen, H. G. Pomp, H. Lifka, and P. H. Woerlee, “Three hot-carrier degradation mechanisms in deep-submicron PMOSFETs,” IEEE Transactions on Electron Devices, vol. 42, no. 1, pp. 109-115, Jan, 1995.
[4] C. L. Lou, W. K. Chim, D. Siu-Hung, and Y. Pan, “A novel single-device DC method for extraction of the effective mobility and source-drain resistances of fresh and hot-carrier degraded drain-engineered MOSFET's,” IEEE Transactions on Electron Devices, vol. 45, no. 6, pp. 1317-1323, Jun, 1998.
[5] S. H. Renn, J. L. Pelloie, and F. Balestra, “Hot-carrier effects and reliable lifetime prediction in deep submicron N- and P-channel SOI MOSFET's,” IEEE Transactions on Electron Devices, vol. 45, no. 11, pp. 2335-2342, Nov, 1998.
[6] S. Mahapatra, C. D. Parikh, V. R. Rao, C. R. Viswanathan, and J. Vasi, “Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFET's,” IEEE Transactions on Electron Devices, vol. 47, no. 4, pp. 789-796, Apr, 2000.
[7] M. Saxena, S. Haldar, M. Gupta, and R. S. Gupta, “Physics-based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency,” IEEE Transactions on Electron Devices, vol. 49, no. 11, pp. 1928-1938, Nov, 2002.
[8] M. J. Kumar, and A. Chaudhry, “Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs,” IEEE Transactions on Electron Devices, vol. 51, no. 4, pp. 569-574, Apr, 2004.
[9] R. Bellens, P. Heremans, G. Groeseneken, and H. E. Maes, “On the channel-length dependence of the hot-carrier degradation of n-channel MOSFETS,” IEEE Electron Device Letters, vol. 10, no. 12, pp. 553-555, Dec, 1989.
[10] R. Bellens, G. Groeseneken, P. Heremans, and H. E. Maes, “Hot-carrier degradation behavior of n-channel and p-channel MOSFETs under dynamic operation conditions,” IEEE Transactions on Electron Devices, vol. 41, no. 8, pp. 1421-1428, Aug, 1994.
[11] E. H. Li, and S. Prasad, “Channel width dependence of NMOSFET hot carrier degradation,” IEEE Transactions on Electron Devices, vol. 50, no. 6, pp. 1545-1548, Jun, 2003.
[12] J. F. Chen, K. M. Wu, J. R. Lee, Y. K. Su, H. C. Wang, Y. C. Lin, and S. L. Hsu, “Characteristics and improvement in hot-carrier reliability of sub-micrometer high-voltage double diffused drain metal-oxide-semiconductor field-effect transistors,” Japanese Journal of Applied Physics Part 1-Regular Papers Brief Communications & Review Papers, vol. 46, no. 4B, pp. 2019-2022, Apr, 2007.
[13] E. Takeda, and N. Suzuki, “An empirical model for device degradation due to hot-carrier injection,” IEEE Electron Device Letters, vol. 4, no. 4, pp. 111-113, 1983.
[14] H. Chenming, C. T. Simon, H. Fu-Chieh, K. Ping-Keung, C. Tung-Yi, and K. W. Terrill, “Hot-electron-induced MOSFET degradation—Model, monitor, and improvement,” IEEE Transactions on Electron Devices, vol. 32, no. 2, pp. 375-385, 1985.

chapter 7 references
[1] H. Chenming, C. T. Simon, H. Fu-Chieh, K. Ping-Keung, C. Tung-Yi, and K. W. Terrill, "Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement," IEEE Journal of Solid-State Circuits, vol. 20, no. 1, pp. 295-305, 1985.
[2] D. Varghese et al., "off-State Degradation in Drain-Extended NMOS Transistors: Interface Damage and Correlation to Dielectric Breakdown," IEEE Transactions on Electron Devices, vol. 54, no. 10, pp. 2669-2678, 2007.
[3] D. Varghese, P. Moens, and M. A. Alam, "on-State Hot Carrier Degradation in Drain-Extended NMOS Transistors," IEEE Transactions on Electron Devices, vol. 57, no. 10, pp. 2704-2710, 2010.
[4] D. Varghese, M. A. Alam, and B. Weir, "A generalized, IB-independent, physical HCI lifetime projection methodology based on universality of hot-carrier degradation," in 2010 IEEE International Reliability Physics Symposium, 2010, pp. 1091-1094.
[5] D. Varghese, G. Mathur, V. Reddy, J. Heater, and S. Krishnan, "Simulation and modeling of hot carrier degradation of cascoded NMOS transistors for power management applications," in 2012 IEEE International Reliability Physics Symposium (IRPS), 2012, pp. 3B.3.1-3B.3.4