| 研究生: |
王兆汯 Wang, Chao-Hung |
|---|---|
| 論文名稱: |
相異輕摻雜區濃度之高壓金氧半場效電晶體其熱載子可靠度壽命預測之研究 Hot Carrier Reliability Lifetime Prediction of High Voltage MOSFET for Different Lightly Doped Drain Doping Concentration |
| 指導教授: |
陳志方
Chen, Jone-Fang |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 微電子工程研究所 Institute of Microelectronics Engineering |
| 論文出版年: | 2021 |
| 畢業學年度: | 109 |
| 語文別: | 英文 |
| 論文頁數: | 121 |
| 中文關鍵詞: | 高壓金氧半場效電晶體 、比例係數 、輕摻雜汲極 、熱載子導致之退化 、電腦輔助設計模擬 |
| 外文關鍵詞: | HV-MOSFET, scaling factor, LDD, hot-carrier-induced degradation, TCAD simulation |
| 相關次數: | 點閱:236 下載:0 |
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在本論文中, 我們針對N型通道高壓金氧半場效電晶體 (HVMOSFET) 的特性以及熱載子可靠度壽命預測進行研究,同時也近一步討論不同輕摻雜汲極 (Lightly Doped Drain) 濃度元件之可靠度並討論其壽命預測曲線。
首先,簡單描述本論文的研究動機並介紹高壓金氧半場效電晶體元件在現代生活中的應用與其優點特色。眾所周知高壓元件具有高操作電壓的環境,因此隨著高壓元件被大量使用其熱載子可靠度及其壽命預測是近年來相當重要的議題,我們將簡單介紹熱載子效應和元件結構及基本電性的量測。其中包括元件結構與定義內部區域並且描述元件的量測條件與方法,其中包含:元件電流ID-VG、ID-VD、基板電流ISUB-VG之量測以及TCAD模擬之校準。此外在電腦輔助設計(TCAD)模擬的幫助下我們能更深入了解元件內部的物理機制。
在本論文中所討論的元件壽命是透過名為比例係數(Scaling Factor)的方法所得到的。在過去的研究中指出,長時間的退化特性可以由短時間的加速測試而得到,而退化曲線遵循著相似的趨勢,藉由平移曲線可重疊各曲線並形成通用退化曲線,此平移之倍率我們稱為比例係數(Scaling Factor)。因此藉由觀察通用曲線及比例係數我們可以預估元件壽命。
在第三章中我們將元件壽命對ISUB作圖,同時比較了HV-MOSFET與LV-MOSFET的差異。發現兩者呈現不圖的幂律指數,先前研究中已指出當不同載子主導退化時將呈現不同的幂律指數。然而HV-MOSFET在高汲極電壓時我們觀察到不同以往的幂律指數。因此我們將利用TCAD模擬結果給予其合理的解釋。
最後,我們分析不同輕摻雜汲極濃度元件之特性並藉由TCAD模擬來解釋為何當HV-MOSFET在高閘極電壓時幂律指數也將隨不同輕摻雜汲極濃度而有所改變。
In this thesis, we study the characteristics of N-channel high-voltage metal oxide semiconductor field effect transistors (HVMOSFET) and the prediction of hot carrier reliability lifetime, and also discuss the different lightly doped drain concentrations. The reliability of the device and its lifetime prediction curve are discussed.
First, briefly describe the research motivation of this paper and introduce the application of high-voltage MOSFET devices in modern lifetime and their advantages and characteristics. It is well known that high-voltage devices have a high operating voltage environment. Therefore, as high-voltage devices are widely used, their hot carrier reliability and lifetime prediction are very important issue in recent years. We will briefly introduce the hot carrier effect, device structure, and basic electrical characteristic measurement. Including the device structure and defining the internal area and describing the measurement conditions and methods of the device, including device current ID-VG, ID-VD, substrate current ISUB-VG measurement, and TCAD simulation calibration. In addition, with the help of computer-aided design (TCAD) simulation, we can have a deeper understanding of the internal physical mechanism of the device.
The lifetime of the device discussed in this paper is obtained through a method called Scaling Factor. In previous studies, it was pointed out that long-term degradation characteristics can be obtained by short-term accelerated testing, and the degradation curve follows a similar trend. By shifting, the curves overlap and form a universal degradation curve. The magnification of this translation is called the scaling factor (Scaling Factor). Therefore, we can estimate the lifetime of the device by observing the universal curve and the scaling factor.
In Chapter 3, we plot the device lifetime against ISUB and compare the differences between HV-MOSFET and LV-MOSFET. It is found that the two show different power-law exponents. Previous studies have pointed out that different power-law exponents will appear when different carriers dominate the degradation. However, we observe a different power-law exponent when the stress of the HV-MOSFET is at a high drain voltage. Therefore, we will use the TCAD simulation results to give a reasonable explanation.
Finally, we analyze the characteristics of different lightly doped drain concentration devices and use TCAD simulation to explain why the power-law exponent will also change with different lightly doped drain concentrations when the HV-MOSFET stress at a high gate voltage.
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