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研究生: 林志展
Lin, Chih-Chan
論文名稱: 延遲隱藏式晶片外記憶體保護使用基於物理不可複製函數之安全微系統
Latency-Hiding Off-chip Memory Protection using PUF-based Secure Microsystem
指導教授: 邱瀝毅
Chiou, Lih-Yih
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2021
畢業學年度: 109
語文別: 中文
論文頁數: 41
中文關鍵詞: 硬體安全 、物理不可複製函數 、晶片外記憶體 、物聯網裝置
外文關鍵詞: Hardware security, Physical Unclonable Function (PUF), Off-chip memory, Internet of Thing (IoT) device
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  • 近年來物聯網裝置逐漸普及與人工智慧技術的發展,兩者結合而成的智慧物聯網(AIoT)也開始被廣泛的討論。物聯網裝置透過感測器從環境進行感測,將收集的資料儲存於晶片外記憶體中,再利用邊緣運算進行機器學習的推論,最後將結果回傳至伺服器端。隨著智慧物聯網的發展,裝置的安全與隱私將和人身、公共安全息息相關。為了確保科技的進步不會成為攻擊者侵害權益的手段,因此需要針對物聯網裝置的硬體安全機制進行研究與探討。
    本論文提出一個針對晶片外記憶體進行保護之使用物理不可複製函數為基礎的安全微系統,此微系統以應用於物聯網裝置為發想設計,並於微系統中提出針對晶片外記憶體之保護與隱藏延遲之機制。此平台包含安全模組,透過安全模組與物理不可複製函數(PUF)提供之金鑰來進行保護機制。

    In recent years, Internet of Things (IoT) devices become popular and artificial intelligence (AI) technology is developing rapidly. As a result, the combination of these two technologies called artificial intelligence of things (AIoT) is being widely discussed. IoT devices use sensors to sense from the environment and store the collected data in off-chip memory. The devices then use edge computing to do machine learning inference and return the results back to the server. With the development of the smart IoT, the security and privacy of devices are relevant to personal and public safety. As a result, hardware security mechanisms for IoT devices becomes more important than ever before.

    In this work, we propose a secure microsystem based on PUF with off-chip memory protection. Furthermore, we propose a mechanism that can effectively hide the latency caused by protection calculations while ensuring security. The platform includes a security module and provides protection through the security module and the key provided by the PUF.

    摘 要 i ABSTRACT ii 目錄 x 表目錄 xiI 圖目錄 xiII 第1章 緒論 1 1.1 研究概觀 1 1.2 研究動機 2 1.3 研究貢獻 4 1.4 論文架構 4 第2章 相關研究背景 5 2.1 物理不可複製函數 5 2.2 進階加密標準 7 2.3 晶片外記憶體的攻擊與防護方法 10 2.3.1 對晶片外記憶體的攻擊簡介 10 2.3.2 對晶片外記憶體的防護方案 12 第3章 相關文獻探討 13 3.1 資料竄改之防護與偵測 13 3.2 驗證效能之改善 15 3.3 利用物理不可複製函數進行完整性驗證 16 3.4 相關文獻總結 18 第4章 輕量級微系統之硬體安全性設計探勘 19 4.1 微系統架構 19 4.1.1 記憶體保護元件與周邊鎖 20 4.2 晶片外記憶體防護與效能改善機制 22 4.2.1 晶片外記憶體防護機制 22 4.2.2 晶片外記憶體效能改善機制 25 第5章 實驗結果與分析 28 5.1 實驗環境設置 28 5.2 實驗一、使用安全推測資料取用機制對系統效能之影響 30 5.2.1 實驗目標與參數設定 30 5.2.2 實驗結果 31 5.3 實驗二、使用安全推測資料取用機制對系統之效能懲罰 36 5.3.1 實驗目標與參數設定 36 5.3.2 實驗結果 36 第6章 結論與未來研究 38 6.1 結論 38 6.2 未來工作 39 參考文獻 40

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