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研究生: 林聖凱
Lin, Sheng-Kai
論文名稱: 可抵禦滿足性攻擊且具有硬體模糊技術之物理密鑰為本的安全微型系統
Satisfiability Attack Resilient Physical Unclonable Function-based Secure Microsystem with Hardware Obfuscation
指導教授: 邱瀝毅
Chiou, Lih-Yih
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2021
畢業學年度: 109
語文別: 中文
論文頁數: 65
中文關鍵詞: 硬體安全 、物理密鑰 、進階加密標準 、滿足性攻擊 、硬體模糊
外文關鍵詞: Hardware security, Physical Unclonable Function(PUF), Advanced Encryption Standard, Satisfiability attack, Hardware obfuscation
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  • 近年來全球化的晶片產業鏈逐漸發展成熟,不同的產業聚落散佈在世界各地。雖然專業分工帶來更多的利益,但同時這種合作關係也會導致智慧財產(Intellectual Property, IP)暴露在危險之中,如何確保智慧財產不被竊取成為一個重要的議題。傳統的硬體模糊技術雖然能夠抵擋竊取硬體架構為目的的攻擊,但是硬體模糊技術本身需要改善所有相同設計的晶片使用同一組金鑰的問題,除此之外,針對硬體模糊技術而發明的滿足性攻擊(Satisfiability attack, SAT attack)能夠在短時間能破解出傳統的硬體模糊設計的金鑰,因此需要針對此攻擊研發新型態的硬體模糊技術。
    本論文提出的使用硬體模糊技術之安全微型系統,只要付出有限的面積成本提升金鑰的長度就能大幅增加滿足性攻擊破解所需要的遞迴次數和耗時。金鑰的生產流程中,除了運用物理密鑰(Physical Unclonable Function, PUF)使每一個晶片都有自己獨一無二的金鑰組之外,也使用進階加密標準(Advanced Encryption Standard, AES)進行後處理,使物理密鑰的挑戰響應對不會因此而外洩,避免造成安全性的破口。系統的開機流程也經過設計,在安全模式下可以不受硬體模糊設計的影響,進行系統測試與物理密鑰的量測;在一般模式下,需輸入硬體模糊設計的金鑰,才能正確啟動。

    In recent years, the global IC industry has gradually matured. Although the vertical international specialization brings more benefits, this kind of partnership will expose intellectual property (IP) to danger at the same time. Protecting the valuable IP becomes a serious problem. Using the conventional hardware obfuscation technology can prevent the IP from the hardware-based piracy, but the problem of using the same set of keys needs to be solved. Furthermore, the satisfiability attack against hardware obfuscation technology is invented. Therefore, a state-of-the-art hardware obfuscation technology solved the problem stated above is needed.
    In this work, we proposed a satisfiability attack resilient physical unclonable function-based secure microsystem with hardware obfuscation. It increases the number of iterations and time needed for the satisfiability attack substantially with a limited area overhead. In the production process of the key, a chip using physical unclonable function (PUF) processes a unique set of keys. Furthermore, we can prevent the challenge-response pairs from leaking by using AES to encrypt as the post-processing. Also, the booting process has been re-designed to accommodate the hardware obfuscation. In secure mode, the measurement of system and PUF can be done without the activation of the hardware obfuscation. In normal mode, activating with the correct key of the hardware obfuscation is necessary to boot successfully.

    摘要 i ABSTRACT ii 誌謝 vii 目錄 viii 表目錄 x 圖目錄 xi 第1章 緒論 1 1.1 研究概觀 1 1.2 研究動機 4 1.3 研究貢獻 6 1.4 論文架構 6 第2章 相關研究背景 7 2.1 物理密鑰 7 2.2 進階加密標準 10 2.3 生產鏈攻擊與可信任技術 16 2.3.1 生產鏈攻擊的種類簡介 16 2.3.2 可信任技術的種類簡介 18 第3章 相關文獻探討 21 3.1 針對硬體模糊技術之滿足性攻擊 21 3.2 防禦滿足性攻擊之硬體模糊技術 24 3.2.1 防禦滿足性攻擊模組 24 3.2.2 功能喪失邏輯鎖 29 3.3 使用巨量級物理密鑰之硬體模糊技術 33 3.4 相關文獻總結 37 第4章 具有硬體模糊技術的安全微型系統 39 4.1 微型系統架構 39 4.1.1 安全模組架構 41 4.2 硬體模糊設計 42 4.2.1 使用硬體模糊設計之安全微型系統架構 42 4.2.2 使用物理密鑰與進階加密標準之金鑰生產流程 46 4.2.3 考慮硬體模糊設計的開機流程 47 4.3 攻擊模型與對策 49 4.3.1 設計階段(Design stage) 49 4.3.2 生產階段(Manufacturing stage) 50 4.3.3 使用者階段(Market stage) 50 第5章 實驗結果與分析 51 5.1 分析本論文之硬體模糊設計 51 5.1.1 實驗環境設定 51 5.1.2 實驗結果分析 52 5.2 與其他硬體模糊技術進行比較 55 5.2.1 實驗環境設定 55 5.2.2 實驗結果分析 55 5.3 分析微型系統上的硬體模糊架構 57 5.3.1 實驗環境設定 57 5.3.2 實驗結果分析 57 5.3.3 開機流程 58 第6章 結論與未來研究 61 6.1 結論 61 6.2 未來工作 62 參考文獻 63

    [1] Semiconductor Industrial Association. (2021, May. 20). Global Semiconductor Value Chain Map [Online]. Available: https://www.semiconductors.org/policies/trade/
    [2] M. Yasin, “Towards Provably Secure Logic Locking for Hardening Hardware Security,” Ph.D. dissertation, Dept. Elect. Eng., New York Univ., Brooklyn, NY, 2018
    [3] EPS News. (2021, May 20). Fabless Chip Makers Gain Share in Global IC Market [Online]. Available: https://epsnews.com/2020/12/28/fabless-chip-makers-gain-share-in-global-ic-market/
    [4] J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, “Security analysis of integrated circuit camouflaging,” in Proceedings of the ACM Conference on Computer and Communications Security, vol. 1120, no. d, pp. 709–720, 2013.
    [5] R. Jarvis and M. McIntyre, “Split Manufacturing Method for Advanced Semiconductor Circuits,” U.S. Patent 7 195 931, May 27, 2004
    [6] F. Koushanfar, “Provably secure active IC metering techniques for piracy avoidance and digital rights management,” IEEE Transactions on Information Forensics and Security, vol. 7, no. 1 PART 1, pp. 51–63, 2012.
    [7] J. A. Roy, I. B. M. Corp, F. Koushanfar, and I. L. Markov, “Ending piracy of integrated circuits,” Computer, vol. 43, no. 10, pp. 30–38, 2010.
    [8] P. Subramanyan, S. Ray, and S. Malik, “Evaluating the security of logic encryption algorithms,” in Proceedings of the 2015 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2015, pp. 137–143, 2015.
    [9] B. Rothke, “A look at the Advanced Encryption Standard (AES),” Information Security Management Handbook, Sixth Edition, pp. 1151–1158, 2007.
    [10] C. Herder, M. D. Yu, F. Koushanfar, and S. Devadas, “Physical unclonable functions and applications: A tutorial,” Proceedings of the IEEE, vol. 102, no. 8, pp. 1126–1141, 2014.
    [11] C. H. Chang, Y. Zheng, and L. Zhang, “A Retrospective and a Look Forward: Fifteen Years of Physical Unclonable Function Advancement,” IEEE Circuits and Systems Magazine, vol. 17, no. 3, pp. 32–62, 2017.
    [12] WIKIPEDIA, “Advanced Encryption Standard,” 2021 [Online]. Available: https://en.wikipedia.org/wiki/Advanced_Encryption_Standard.
    [13] CSDN, “Cypher Algorithm Introduction – AES,” 2015 [Online]. Available: https://blog.csdn.net/Aeroleo/article/details/49738837.
    [14] WIKIPEDIA, “Block cipher mode of operation,” 2021 [Online]. Available: https://en.wikipedia.org/wiki/Block_cipher_mode_of_operation.
    [15] WIKIPEDIA, “Galois/Counter Mode,” 2021 [Online]. Available: https://en.wikipedia.org/wiki/Block_cipher_mode_of_operation.
    [16] M. Rostami, F. Koushanfar, and R. Karri, “A primer on hardware security: Models, methods, and metrics,” Proceedings of the IEEE, vol. 102, no. 8, pp. 1283–1295, 2014.
    [17] J. Rajendran, H. Zhang, C. Zhang, G. S. Rose, Y. Pino, O. Sinanoglu, and R. Karri, “Fault Analysis-Based Logic Encryption,” IEEE Transactions on Computers, vol. 64, no. 2, pp. 410–424, 2015.
    [18] M. Yasin, J. J. Rajendran, O. Sinanoglu, and R. Karri, “On Improving the Security of Logic Locking,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 9, pp. 1411–1424, 2016.
    [19] Y. Xie and A. Srivastava, “Anti-SAT: Mitigating SAT Attack on Logic Locking,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 2, pp. 199–207, 2019.
    [20] M. Yasin, A. Sengupta, M. T. Nabeel, M. Ashraf, J. Rajendran, and O. Sinanoglu, “Provably-Secure logic locking: From theory to practice,” in Proceedings of the ACM Conference on Computer and Communications Security, no. i, pp. 1601–1618, 2017.
    [21] S. Khaleghi and W. Rao, “Hardware obfuscation using strong PUFs,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2018-July, pp. 321–326, 2018.
    [22] Anon. (1985). ISCAS85 Combinational Benchmark Circuits [Online]. Available: https://filebox.ece.vt.edu/~mhsiao/iscas85.html
    [23] J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, “Security analysis of logic obfuscation,” in Proceedings of Design Automation Conference, 2012, pp. 83-89.
    [24] J. Rajendran, Y. Pino, O. Sinanoglu and R. Karri, “Logic encryption: A fault analysis perspective,” in Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, pp. 953-958.

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