本論文中，使用TSMC 0.35um 2P4M mixed signal CMOS製程來實現一個可應用在IEEE 802.11a 無線區域網路之10位元100MS/s電流導向數位類比轉換器。此架構中，最大六個有效數位碼轉成溫度計碼，最小四個有效數位碼使用二進位權重碼。在電流單元設計上，評估適當的電流源面積克服製程變動造成的元件不匹配，電流源與電流開關採用疊接架構提升轉換器性能，如INL與SFDR特性。另外，低交越點開關驅動器避免電流開關同時關閉減少突波，且在電流源矩陣使用特殊佈局方法降低系統誤差。
模擬顯示，在靜態特性上：微分非線性誤差小於±0.2 LSB，積分非線性誤差小於±0.25 LSB。當取樣頻率100MHz，輸入信號2MHz與30MHz時，無突波動態範圍(SFDR)為68.2dB與58.3dB，功率消耗在數入訊號30MHz時消耗78.4mW，整個晶片面積2.1mm2

In this thesis, a 10-bit 100M-Sample/s current steering digital-to-analog for WLAN is proposed. It is implemented in TSMC 0.35um 2P4M mixed signal CMOS technology. Segmented current steering architecture that comprises 6MSB’s thermometer code structure and 4LSB’s binary-weighted one is applied in this design. In the current cell, proper area of current source is evaluated to overcome mismatch error due to process variation. Cascoded current source and cascoded switch are adapted to improve the performance of the DAC, such as INL and SFDR. In addition, a low cross point driver which avoids the switches to cut off at the same time is designed to reduce glitch error. Special layout techniques are used to minimize systematic error in current source array.
The simulation results show that DNL is less than ±0.2 LSB and INL is less than ±0.25 LSB. For a 100MHz update, the SFDR is 68.2dB at 2MHz signal frequency and the SFDR is 58.3dB at 30MHz signal frequency. The power consumption is 78.4mW at a 30MHz input signal with 100MHz update rate. The total area is 2.1mm2.

[1] D. Zargari, et al, “A 5-GHz CMOS Transceiver for IEEE 802.11a Wireless LAN System,” IEEE J. So