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研究生: 吳倚彰
Wu, Yi-Jang
論文名稱: 應用串列式編碼架構降低晶片匯流排的串音效應
Serial Bus Coding Schemes for Cross-talk Reduction in On-Chip Bus
指導教授: 郭致宏
Kuo, Chih-Hung
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2006
畢業學年度: 94
語文別: 中文
論文頁數: 83
中文關鍵詞: 向量匯流排編碼串音效應耦合電容增速封包
外文關鍵詞: packet, speed-up, coupling-capacitance, crosstalk, bus coding, vector
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  • 由於製程的進步導致串音效應愈來愈嚴重,造成晶片內部連接線延遲,並且限制了系統效能。傳統降低串音效應的編碼方法,會造成較大的匯流排面積。所以在本論文中,提出了以封包為處理單位的串列式編碼。它的編碼方法是以增加傳送向量數量的方式,來達到降低匯流排面積的目的。我們設計各種不同的串列式編碼演算法與電路,來降低串音效應。且使用HSPICE來模擬並測量匯流排上的消耗能量與訊號傳遞延遲,以及使用0.18-μm CMOS standard cell library 來估計編解碼器的面積與延遲。

    The crosstalk delay becomes more and more serious due to advanced technology, and it limits the performance of system. In the past literatures some coding methodologies have been proposed to reduce crosstalk, but they will result in a serious bus area overhead. In this paper, we propose a serial coding methodology that encodes a packet at once. This coding methodology increases transmitted number of patterns to reduce bus area and we propose various coding algorithms and circuits that reduce crosstalk effect. Delay and energy dissipation on the bus are obtained using HSPICE. Delay and area of the codec are estimated using 0.18-μm CMOS standard cell library.

    摘要.......................................I Abstract...................................II 誌謝.......................................III 內容.......................................IV 表目次.....................................VI 圖目次.....................................VII 第一章、 介紹..............................1 1.1研究動機................................1 1.2研究目標................................1 1.3背景知識................................2 1.4論文架構................................4 第二章、 相關預防串音效應編碼方法..........6 2.1耦合係數p=2的編碼方法...................8 2.2耦合係數p=3的編碼方法...................19 2.3耦合係數p=1的編碼方法...................22 2.4訊號轉換與消耗能量之間關係的分析........25 第三章、 串列式編碼的方法與效率分析........29 3.1介紹....................................29 3.2 C(2, n, l)碼...........................36 3.3 C(3, n, l)碼...........................38 3.4 C(1, n, l)碼...........................39 3.5編碼效率................................40 第四章、 串列式編碼硬體架構與實驗結果......48 4.1 匯流排延遲為(1+2λ)τ0的串列式編碼架構...48 4.2 匯流排延遲為(1+3λ)τ0的串列式編碼架構...53 4.3 匯流排延遲為(1+λ)τ0的串列式編碼架構....57 4.4 模擬結果...............................63 第五章、 結論..............................72 附錄 1.....................................74 附錄 2.....................................76 附錄 3.....................................79 參考文獻...................................82

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