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研究生：	巫浚賢 Wu, Chun-Hsien
論文名稱：	具低輸出電壓漣波之升降壓型直流-直流轉換器 A Step-Up/Step-Down DC-DC Converter with Low Output Voltage Ripple
指導教授：	魏嘉玲 Wei, Chia-Ling
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	中文
論文頁數：	107
中文關鍵詞：	升降壓、直流轉換器、穩壓器、低輸出電壓漣波
外文關鍵詞：	step-up/step-down, DC-DC converter, regulator, low output voltage ripple
相關次數：	點閱：101 下載：11
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近年來由於可攜式電子產品的蓬勃發展，需要以電池當做電源供應主要來源。但由於電池的電壓會隨著使用時間而逐漸下降，電子產品會因而受到影響，造成功效不彰甚至無法運作。因此，需要直流-直流電壓轉換器將隨時間改變的電池電壓維持在系統所需穩定電壓。本晶片可將輸入電壓(2.5V、5V)轉換成固定的輸出電壓(3.3V)。本轉換器實際上屬於將一可升降壓型充電式電荷泵浦與一低壓降線性穩壓器作結合。由於類比電路對於漣波雜訊很敏感，而低壓降線性穩壓器的特性可有效地抑制充電式電荷泵浦的輸出雜訊。
研究晶片是透過國家晶片系統設計中心提供的製程服務，使用台灣積體電路公司0.35μm 2P4M 5V混合訊號製程，以32 S/B封裝，尺寸為1.4×1.4mm2。根據量測的結果，本晶片除了能夠將2.5到5伏特的輸入電壓轉換成穩定的3.3伏特電壓輸出，亦能具有低輸出電壓漣波。能量轉換效率則接近理論值。充電式電荷泵浦之線性調節率為12.9mV/V與0.23V/V(升壓與降壓)，負載調節率約為1mV/mA;低壓降線性穩壓器之線性調節率為0.8mV/V，負載調節率為0.294mV/mA。

More and more battery-powered portable electronic products are introduced to the market in recent years. However, since the battery voltage typically decreases with time, a DC-DC converter is required to convert the time-varying battery voltage to a stable output voltage for the electronic circuits. This work implemented a versatile step-up/step-down dc-dc converter, which can convert a varied input voltage to a fixed 3.3V output voltage. The converter actually consists of a charge-pump-based converter and a low dropout regulator (LDO). Because a clean supply voltage is required for analog circuits, the LDO is included to effectively suppress the output voltage ripple of the charge-pump-based converter.
The die area of the testchip is 1.4×1.4mm2. The chip was implemented by Taiwan Semiconductor Manufacturing Company (TSMC) 0.35μm 2P4M 5V mixed-signal polycide process, patronized by National Chip Implementation Center (CIC). According to the measured result, its input voltage range is 2.5-5 V, and its output voltage ripple is ultra low. The power efficiency is theoretical value approximately. The line regulation of charge-pump converter stage is 12.9mV/V (step-up mode) and 0.23V/V (step-down mode). The load regulation of charge-pump converter stage is about 1mV/mA. The line regulation of LDO stage is 0.8mV/V, and its load regulation is 0.294mV/mA.

第一章	簡介...............................................1
1 研究動機...............................................1
2 論文架構...............................................3
第二章	背景資料...........................................4
1 充電式電荷泵浦(Charge Pump)............................4
1.1 降壓型充電式電荷泵浦.................................4
1.2 升壓型充電式電荷泵浦.................................8
1.2.1基本的倍壓電荷泵浦電路..............................9
1.2.2 雙相電荷泵浦(TPVD).................................9
1.2.3 Makowski電荷泵浦..................................10
1.2.4 多相電荷泵浦......................................10
1.2.5 具調節機制之升壓型充電式電荷泵浦..................11
1.3 升降壓型充電式電荷泵浦..............................15
2 低壓降線性穩壓器(Low Dropout Linear Regulator, LDO)...19
2.1 低壓降線性穩壓器電路運作簡介........................19
2.2 低壓降線性穩壓器穩定度分析..........................19
2.3 電壓緩衝器補償......................................21
2.4 巢狀米勒電容補償 (Nested Miller Compensation, NMC)..22
2.5 內部電容零點補償....................................23
2.6 壓控電流源補償......................................25
第三章	電路設計..........................................28
1電路架構...............................................28
2主要電路分析...........................................29
2.1 電路操作............................................29
2.2 效率推算............................................29
2.2.1 升降壓充電式電荷泵浦效率推算......................30
2.2.2 低壓降線性穩壓器效率推算..........................33
2.2.3 全電路效率推算....................................34
2.3 穩定度分析..........................................34
3 升降壓充電式電荷泵浦之回授控制電路....................39
3.1 回授控制電路說明....................................39
3.2 切換式電容電路......................................40
3.3 運算放大器與偏壓電路................................42
3.4 軟啟動電路..........................................44
4 帶參電路..............................................45
5 時脈電路..............................................47
5.1 時脈產生電路........................................47
5.2 時脈選擇電路........................................49
5.2.1 比較器電路........................................49
5.2.2 電壓提昇電路......................................50
5.2.3 非重疊時脈產生器..................................51
5.2.4 延遲產生電路......................................52
5.2.5 時脈選擇電路的操作................................53
6 低壓降線性穩壓器之補償電路............................55
第四章	模擬與佈局........................................58
1 模擬結果..............................................58
1.1 電路區塊模擬........................................58
1.2 系統暫態響應模擬....................................65
1.3 負載電流變動模擬....................................74
2 佈局..................................................79
第五章	量測結果..........................................81
1 量測儀器..............................................81
2 量測結果..............................................82
第六章	結論.............................................105
參考文獻.................................................106
                                    

[1] B. Robert Gregoire, “A Compact Switched-Capacitor Regulated Charge Pump Power Supply,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1944-1953, Aug. 2006.
[2] J. Han, A. von Jouanne, and G. C. Temes, “A New Approach to Reducing Output Ripple in Switched-Capacitor-Based Step-Down DC-DC Converters,” IEEE IAS, vol. 2, pp. 1115–1120, Oct. 2004.
[3] S. Bin, Y. Yujia, W. Ying, and H. Zhiliang,” High Efficiency, Inductorless Step-Down DC/DC Converter,” IEEE ASICON 2005, vol. 1, pp. 395-398, Oct. 2005.
[4] M. S. Makowski, “Realizability Conditions and Bounds on Synthesis of Switched-Capacitor DC–DC Voltage Multiplier Circuits,” IEEE Trans. Circuits Syst. I, vol. 44, pp. 684–691, Aug. 1997.
[5] J. A. Starzyk, Y. W. Jan, and F. Qiu, ”A DC-DC Charge Pump Design Based on Voltage Doublers,” IEEE Trans. Circuits Syst. I, vol. 48, pp. 350-359, Mar. 2001.
[6] Y. W. Lu, G. Feng, Y. F. Liu, “A Large Signal Dynamic Model for DC-to-DC Converters with Average Current Control,” IEEE APEC ‘04, vol. 2, pp. 797-803.
[7] David Johns and Ken Martin, “Analog Integrated Circuit Design”, John Wiley & Sons, Inc., 1997.
[8] Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, McGraw-Hill Education, 2002.
[9] Chaitanya K. Chava and José Silva-Martínez, “A Frequency Compensation Scheme for LDO Voltage Regulators,” IEEE Trans. Circuits Syst.,vol.51,no.6,June 2004.
[10] Sai Kit Lau, Ka Nang Leung, and Philip K. T. Mok, “Analysis of Low-Dropout Regulator Topologies for Low-Voltage Regulation,” Electron Devices and Solid-State Circuits, 2003 IEEE Conference on 16-18 Dec. 2003, 379-382
[11] Chia-Ling Wei, Lu-Yao Wu, Hsiu-Hui Yang, Chien-Hung Tsai, Bin-Da Liu and Soon-Jyh Chang, “A versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter,” IEICE TRANS. ELECTRON., vol.E91-C,no.5 May 2008.
[12] Hyunho Chu, Jungmoon Kim and Chulwoo Kim, “A monolithic voltage-mode DC-DC converter with a novel oscillator and ramp generator,” IEICE Electronics Express, vol.5, no.17,683-688.

校內：2012-08-25公開
校外：2012-08-25公開

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