依序最佳化(Sequential Minimal Optimization, SMO)是目前應用於語者辨識領域最常被使用的一種分類演算法，但是目前艱鉅困難的挑戰是如何縮短過長的訓練時間，本篇論文提出了可重組式硬體架構去改善依序最佳化過長的訓練時間，可重組式硬體架構是將分散式運算和管線化運算整合的一種架構，並且同時擁有分散式運算的高效率和管線化加速的能力，在語音辨識很適合運算高維度特徵。
本篇論文最主要的貢獻在於最佳化硬體設計層級於超大型積體電路設計，將可重組式硬體架構的概念應用於超大型積體電路設計實現依序最佳化達到加速和提升硬體使用率，進而縮小面積和達到及時運算的能力，除此之外平行式網狀硬體架運算構擁有高度的彈性與效能，有效節省晶片內記憶體(internal memory)高達75%的面積和減少14%組合邏輯與序向邏輯的面積。

Sequential Minimal Optimization (SMO) is a popular classification algorithm that is greatly applied in speaker recognition. However, the solution of resolving computational bottleneck in training phase is a difficult challenge. In this work, the reconfigurable architecture with an improved SMO algorithm is proposed for solving the problem in text-independent speaker recognition. Our contributions are attributed to the optimal VLSI design form algorithm to architecture level. At architecture level, a novel idea of distributed computing is implemented by the reconfigurable hardware component which combines parallel and pipeline architecture at the same time. The reconfigurable computing is a high flexible and high performance technology. Finally, the experimental results show that the utilization of memory can achieve 75% saving and the hardware resource can reduce 69% than before.

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