成功大學博碩士論文系統

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研究生：	王建章 Wang, Chien-Chang
論文名稱：	雙處理器架構之SoC平台 A Dual RISC Core for SoC Platform
指導教授：	陳中和 Chen, Chung-Ho
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2004
畢業學年度：	92
語文別：	中文
論文頁數：	109
中文關鍵詞：	SoC平台、雙處理平台
外文關鍵詞：	SoC Platform, Dual CPU
相關次數：	點閱：128 下載：6
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在本篇論文中，我們提出了以同質性雙處理器(dual homogeneous processors)的架構來建立結合網路與多媒體應用的SoC平台。同質性雙處理器架構的主要概念是其中一個RISC core處理多媒體應用，而另一個RISC core負責管控整個系統的運作。在基本的架構中，我們整合了Enchanced RISC Machine (ERM9)、SDRAM controller、vectored interrupt controller、AMBA AHB系統與AHB-to-AHB橋接器。其中ERM9處理器是相容於ARMv4指令集且採五級管線架構。此外，為了增進系統的效能，ERM9也整合了第一層的記憶體系統，包含ICache、DCache、write buffer與MMU等。我們利用測試程式來驗證ERM9與系統上其他的單元的是否正確。而這些測試程式是包含JPEG codec、ADPCM codec、mp2 decodec與mp3 decodec在內的七個多媒體應用程式。

在JPEG的多媒體應用中，除了基本的雙處理器系統平台外，我們也整合了Video Input(VI)與Video Output (VO)。此系統平台使用來處理JPEG壓縮之應用。VI與VO都是設計符合ITU-R656的標準視訊介面，其中VI負責視訊輸入，而VO則負責視訊輸出。在JPEG應用的系統架構中，其中一顆RISC core負責視訊資料的處理，而另一顆RISC core負責執行JPEG壓縮程式。兩顆處理器之間的溝通我們是採share memory的機制。此系統已整合其它IP經由多媒體程式驗證成功。從模擬結果，雙處理器的概念是可行的。

In this thesis, we propose a dual homogeneous processor architecture for web-based multimedia application. The key concept in this dual homogeneous processor design is that one RISC core is responsible for processing multimedia computation while the other takes charge of managing the whole system. The baseline platform is implemented by integrating an Enchanced RISC Machine (ERM9) processor, a SDRAM controller, a vectored interrupt controller, an AMBA AHB system, and an AHB-to-AHB bridge. The ERM9 core is a five-stage pipelined RISC which is compatible with ARMv4 ISA. Furthermore, in order to improve performance, the system processor is integrated with the level-one memory system, including ICache, DCache, write buffer, and MMU. The ERM9 core and the other system components are verified by running bench programs. The programs consist of a JPEG encoder, an ADPCM codec, a mp2 decoder, a mp3 decoder, and so on.

For the JPEG application, a media SoC platform is constructed from the baseline platform which integrates with Video Input (VI) and Video Ouput (VO). This platform is meant to process a static JPEG compression. The VI and the VO are designed to fit in with ITU-R656 standard interface and are responsible for video streams input and output repectively. One RISC core in this platform manages video streams while the other takes charge of excuting the JPEG encoding program. The communications between two processors is implemented by a share memory mechanism. From the simulation results, the concept of the proposed dual core platform is feasible.

Abstract in Chinese …………………………………………………………………i
Abstract ………………………………………………………………………………ii
Acknowledgements……………………………………………………………………iii
List of Tables ………………………………………………………………………vi
List of Figures	……………………………………………………………………vii
Chapter 1.	Introduction………………………………………………………1
1.	Motivation……………………………………………………………………2
2.	Contribution of the thesis………………………………………………2
3.	Organization of the thesis………………………………………………3
Chapter 2.	Background…………………………………………………………4
1.	ARM9 Architecture …………………………………………………………4
1.1.	ARM registers ………………………………………………………………4
1.2.	ARM exception ………………………………………………………………5
1.3.	ARM memory model……………………………………………………………6
2.	MP………………………………………………………………………………8
Chapter 3.	Implementation of ERM9 Core…………………………………13
1.	ERM9 Microprocessor………………………………………………………14
1.1.	ERM9 Pipeline Implementation …………………………………………15
1.2.	Instruction implementation ……………………………………………25
1.3.	Exception handle …………………………………………………………38
2.	Level-one memory system…………………………………………………42
2.1.	I-Cache sub system ………………………………………………………44
2.2.	D-Cache sub system ………………………………………………………46
2.3.	MMU sub system ……………………………………………………………52
Chapter 4.	Dual-RISC Core Platform………………………………………55
1.	Architecture ………………………………………………………………56
1.1.	ERM9 Core……………………………………………………………………56
1.2.	AMBA Bus System……………………………………………………………56
1.3.	AHB-to-AHB Bridge…………………………………………………………59
2.	IP Integration ……………………………………………………………62
Chapter 5.	Verification strategy &      Simulation Model  ………64
1.	Verification Strategy……………………………………………………64
1.1.	Algorithm Verification …………………………………………………66
1.2.	Virtual Prototyping Verification ……………………………………66
1.3.	Behavior Verification……………………………………………………67
1.4.	RTL Verification …………………………………………………………71
1.5.	FPGA Verification…………………………………………………………72
2.	Basic dual-core simulation scenario…………………………………73
2.1.	System Boot & Initialization …………………………………………75
2.2.	Memory map …………………………………………………………………77
2.3.	Interrupt handle …………………………………………………………78
2.4.	System Data Input & Output ……………………………………………79
2.5.	Dual ERM9 Core Communication …………………………………………81
Chapter 6.	Simulation Result………………………………………………83
1.	JPEG media application example ………………………………………85
Chapter 7.	Conclusion ………………………………………………………93
1.	Summary………………………………………………………………………93
2.	Future work…………………………………………………………………93
References ……………………………………………………………………………95

                                    

[1] ModelSim SE 5.8，http://www.model.com/。
[2] ImageLinker，自行開發的程式。可以自動產生ERM9系統boot image。
[3] Intel Corporation, “MultiProcessor Specification Version 1.4,” May 1997.
[4] ARM Corporation, “ARM PrimeCell™ Vectored Interrupt Controller (PL190) Technical Reference Manual,” Ref: ARM DDI 0273A, Issued: September 2000.
[5] ARM Corporation, “Example AMBA SYstem User Guide,” Ref: ARM DUI 0092C, Issued: August 1999.
[6] ARM Corporation, “AHB CPU Wrappers Technical Reference Manual,” Ref: ARM DDI 0169B, Issued: May 2001.
[7] ARM Corporation, “ARM PrimeCell® Inter-Processor Communications Module (PL320) Technical Reference Manual,” Ref: ARM DDI 0306B, Issued: 22nd June 2004.
[8] ARM Corporation, “Example AMBA SYstem User Guide,” Ref: ARM DUI 0092C, Issued: August 1999.
[9] ARM Corporation, “ARM Instruction Set Quick Reference Card v2.1,” Ref: QRC0001H, Issued: October 2003.
[10] ARM Corporation, “ARM922T (Rev 0) Technical Reference Manual,” Ref: DDI0184B, Issued: 20 April 2001.
[11] ARM Corporation, “ARM9TDMI (Rev 3) Technical Reference Manual,” Ref: DDI0180A, Issued: 08 March 2000.
[12] ARM Corporation, “ARM Developer Suite - Version 1.2 - Developer Guide,” Ref: DUI0056D, Issued: 23 November 2001.
[13] ARM Corpoation, “ARM Developer Suite - Version 1.2 - Codewarrior IDE Guide,” Ref: DUI0065D, Issued: 23 November 2001.
[14] ARM Corporation, “ARM Developer Suite - Version 1.2 - AXD and armsd Debuggers Guide,” Ref: DUI0066D, Issued: 21 November 2001.
[15] ARM Corporation, “ARM Developer Suite - Version 1.2 - Compilers and Libraries Guide,” Ref: DUI0067D, Issued: 23 November 2001.
[16] ARM Corporation, “ARM Developer Suite - Version 1.2 - Assembler Guide,” Ref: DUI0068B, Issued: 23 November 2001.
[17] ARM Corporation, “ARM ELF File Format,” Ref: DUI0101A, Issued: 11 November 1998.
[18] ARM Corporation, “ARM Developer Suite - Version 1.2 - Linker and Utilities Guide,” Ref: DUI0151A, Issued: 23 November 2001.

校內：立即公開
校外：2004-09-07公開

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