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研究生： 黃建霖
Huang, Chien-Lin
論文名稱： 使用多供應電壓源與多臨界電壓在低功率數位訊號處理之應用的快速排程與指定演算法
A Fast Simultaneous Scheduling and Assignment of Multiple Supply Voltages and Multi-threshold Voltages for Low-Power DSP Applications
指導教授： 邱瀝毅
Chiou, Lih-Yih
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2007
畢業學年度： 95
語文別： 英文
論文頁數： 83
中文關鍵詞： 低功率 、多供應電壓源 、多臨界電壓
外文關鍵詞： Low-Power, Multi-threshold Voltages, Multiple Supply Voltages
相關次數： 點閱：69  下載：3 
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    • 在本論文中，我們提出兩個可同時排程與指定多電壓源與多臨界電壓在高階合成的演算法。此二種演算法的考量可以應用在降低動態與靜態功率的方面。第一種演算法ENSEMBA可以降低功能元件在限制的條件下的動態與靜態功率。第二種演算法AENSEMBA可以降低在限制條件下功能元件的動態與靜態功率，暫存器的動態靜態功率，準位轉換器以及多工器的功率。此二種演算法,可以在使用者給定的時間限制與面積限制下去計算何種排程與各個硬體需要工作在何種供應電壓源與臨界電壓。而ENSEMBA為AENSEMBA的核心基礎，透過ENSEMBA，除了可以給使用者一個初步較快速的排程與指定電壓結果外也可以驗證我們所提出的演算法是有效的。AENSEMBA架構在ENSEMBA之上，AENSEMBA可以比ENSEMBA多處理暫存器，準位轉換器和多工器的部份，而且可以提供比ENSEMBA更多的資訊給IC後端設計的自動化軟體來加速IC設計時間。經過測試ENSEMBA的演算法可以使我們的測試檔在180nm的製程上有20%至41%的能量節省效果、在32nm的製程上有67%至96%的能量節省效果，AENSEMBA的演算法可以使我們的測試檔在180nm的製程上有16%至40%的能量節省效果、在32nm的製程上有65%至95%的能量節省效果。

    In the thesis, we present two fast algorithms for simultaneous scheduling and assignment of multiple supply voltages and multi-threshold voltages in high level synthesis. We consider not only dynamic energy consumption but also static energy consumption for data-dominant applications. The first algorithm uses Energy-Sensitive Move-Based (ENSEMBA) scheduling method to minimize the energy consumption of functional units simultaneously under constraints. The second algorithm, Aggressive Energy-Sensitive Move-Based (AENSEMBA) scheduling, is an enhanced version of ENSEMBA. It can handle energy consumption related to not only functional resources but also registers as well as level converters. The two algorithms can handle the scheduling of operations, the assignment of supply voltages and threshold voltages under user-define timing and area constraints. ENSEMBA is the core base of AENSEMBA, ENSEMBA can give users enough information to schedule operations and assign voltages and it can also prove that our design concept is efficient. AENSEMBA can handle more issues than ENSEMBA and it can give more information to back-end EDA tools to speed up the IC design time. ENSEMBA algorithm can save energy consumption from 20% to 41% for DSP test cases in technology process 180nm and from 67% to 96% for the same DSP test cases in technology process 32nm. AENSEMBA algorithm can save energy consumption from 16% to 40% for 180nm and from 65% to 95% for 32nm.

    LIST OF TABLES vi LIST OF FIGURES vii Chapter 1 Introduction 1 1.1 Design Challenges 1 1.2 Impact of Static Power 2 1.3 High Level Synthesis 4 1.4 Our Objectives 7 1.5 Contributions 8 Chapter 2 Literature Survey 9 2.1 Overview 9 2.1.1 Integer Linear Programming (ILP) 9 2.1.2 Genetics Algorithm 10 2.1.3 Heuristic Algorithms 11 2.2 Level Converter Issue 12 2.3 Multiple Supply Voltages in FPGA 13 2.4 Methods of Multi-threshold Voltages 13 2.5 Basic Scheduling Methods 14 Chapter 3 Proposed Scheduling Algorithm – ENSEMBA 17 3.1 Motivational Example 17 3.2 Terms and Definitions 19 3.3 ENSEMBA Algorithm 27 3.3.1 Initialization and Transformation Phase 28 3.3.2 Scheduling Phase 31 3.3.3 Constraint-Checking Phase 39 3.4 ENSEMBA Example 39 Chapter 4 Proposed Scheduling Algorithm – AENSEMBA 42 4.1 AENSEMBA Flow 44 4.1.1 Scheduling and supply voltage, threshold voltage assignment 45 4.1.2 Register Energy Estimation Phase 49 4.1.3 Resource Binding and Register Binding 50 4.1.4 Constraint-Checking Phase 52 Chapter 5 Experimental Results 53 5.1 Benchmarks and Setup 53 5.2 Results of Technology Process 180nm 54 5.2.1 Result of Technology Process 180nm (PTM) with ENSEMBA 54 5.2.2 Result of Technology Process 180nm (PTM) with AENSEMBA 57 5.3 Results of Technology Process 32nm 60 5.3.1 Result of Technology Process 32nm with ENSEMBA 60 5.3.2 Result of Technology Process 32nm with AENSEMBA 63 Chapter 6 Conclusions 66 Chapter 7 Future Works 67 Chapter 8 Appendix 68 8.1 Predictive Technology Model 68 8.2 Notations for ILP-Based Formulation 69 8.3 Hardware information 72 References 79 自述 83

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