簡易檢索 / 詳目顯示

回結果列表
研究生： 沈易律
Shen, Yi-Lyu
論文名稱： 高效率三角積分調變器與簡化資料加權平均演算法之設計
Design of a High-Efficient Delta-Sigma Modulator and Simplified Data Weighted Averaging Algorithm
指導教授： 劉濱達
Liu, Bin-Da
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2012
畢業學年度： 100
語文別： 英文
論文頁數： 127
中文關鍵詞： 三角積分調變器 、電荷幫浦式架構 、雜訊耦合技術 、低失真架構
外文關鍵詞： Delta-sigma modulator, Charge-pump based, Noise-coupling, Low-distortion
相關次數： 點閱：94  下載：6 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 本論文提出一個創新之三角積分調變器架構與一種簡化資料加權平均演算法。此創新三角積分調變器使用電荷幫浦式三階低失真的架構設計，且加入雜訊耦合與放寬回授路徑時間之技術，以達到高解析度與低功率消耗之特色。在電路實現方面，此調變器內部之積分器使用共享運算放大器技術來更進一步地降低其功率消耗。另外一方面，本論文亦提出一種基於合併電容切換技術之數位類比轉換器的簡化資料加權平均演算法，相較於傳統資料加權平均演算法，此新式演算法可改善三角積分調變器之線性度與降低其電路實現之成本，並且達到低功率消耗之目的。此創新之三階四位元低失真三角積分調變器使用90 nm一層多晶矽九層金屬導線CMOS製程實現。模擬結果顯示，在80 MHz的取樣頻率與超取樣率為16倍的設定下，噪訊比最高可達到79.04 dB且其整體功率消耗僅為1.8 mW，經換算此電路之功率轉換效率為0.05 pJ/conversion，明顯優於目前已發表文獻之結果。

    In this thesis, a proposed delta-sigma modulator and a simplified data weighted averaging algorithm are presented. The proposed delta-sigma modulator is designed in charge-pump based 3rd-order low-distortion topology with noise-coupling and relaxed feedback timing techniques to achieve high-resolution and low-power dissipation feature. In circuit implementation, the OPAMP-sharing technique is employed in the integrators to further reduce the power consumption. In addition, a simplified data weighted averaging (SDWA) algorithm based on merged-capacitor switching DAC is also presented in this thesis. Compared to the conventional DWA algorithm, the proposed SDWA algorithm improves the linearity of the modulator and reduces the cost of the SDWA circuit while maintaining the low-power consumption feature. This 3rd-order 4-bit low-distortion delta-sigma modulator is implemented by 90-nm 1P9M CMOS process. The simulation results show that the peak SNDR is 79.04 dB with sampling frequency of 80 MHz and oversampling ratio (OSR) of 16. The power dissipation is only 1.8 mW and the Figure-of-Merit is 0.05 pJ/conversion, which is much better than other published works.

    Abstract (Chinese) i Abstract (English) iii Acknowledgement v Table of Contents vii List of Tables xi List of Figures xiii Chapter 1 Introduction 1 1.1 Motivation and Contribution 1 1.2 Organization for the Thesis 4 Chapter 2 Fundamental of Delta-Sigma Modulator 5 2.1 Introduction of Analog-to-Digital Converter 5 2.1.1 Nyquist-rate ADC 7 2.1.2 Oversampling-rate ADC 9 2.2 Delta-Sigma Modulator 10 2.2.1 Oversampling feature 10 2.2.2 Noise-shaping feature 14 Chapter 3 A Charge-Pump Based Low-Distortion 3rd-Order Delta-Sigma Modulator with Noise-Coupling Enhancement and Relaxed Feedback Timing Technique 21 3.1 Architecture Consideration 22 3.1.1 Consideration of conventional structures 22 3.1.2 The low-distortion architecture 23 3.1.3 The multi-bit quantizer configuration 25 3.1.4 The low-distortion architecture with relaxed feedback path timing 28 3.1.5 The noise-coupling enhancement technique 30 3.2 The Charge-Pump Based Switched-Capacitor Integrator 34 3.2.1 Introduction of the conventional charge-pump based switched-capacitor integrator 34 3.2.2 Introduction of the proposed charge-pump based switched-capacitor integrator 38 3.3 Circuit Implementation 42 3.3.1 Parasitic-insensitive charge-pump based integrator 42 3.3.2 Telescopic OPAMP adopted in the 1st and 2nd stages 47 3.3.3 4-bit cyclic-ADC quantizer with adopted active adder 55 3.3.4 Telescopic OPAMP adopted in the cyclic-ADC quantizer 62 3.3.5 The 1.5-bit and 2-bit sub-ADC adopted in cyclic ADC 66 3.3.6 Register and digital error correction circuit 69 3.3.7 Clock generator 73 3.3.8 Complete circuit diagram 75 3.4 Simulation Results and Measurement Environment 77 3.4.1 Simulation results 77 3.4.2 Layout consideration 83 3.4.3 Measurement environment 85 Chapter 4 Simplified Data Weighted Averaging Algorithm Based on Merged-Capacitor Switching DAC Array 87 4.1 Introduction of Conventional Data Weighted Averaging Algorithm 88 4.2 Introduction of Proposed DAC with Merged-Capacitor Switching 90 4.3 Simplified Data Weighted Averaging Algorithm Based on Merged- Capacitor Switching DAC Array 94 4.4 Circuit Implementation 97 4.4.1 Two’s complement correction circuit 99 4.4.2 Point generator and decoder 101 4.4.3 Binary-to-thermometer code converter 103 4.4.4 Barrel shifter 105 4.4.5 Selecting control-signals logic 107 4.5 Microphotograph and Simulation Results 108 4.5.1 Microphotograph and floor-plan 108 4.5.2 Simulation results 109 Chapter 5 Conclusions and Future Work 113 5.1 Conclusions 113 5.2 Future Work 115 References 117 Patent and Awards 125 Biography 127

    [1] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. New York: Oxford, 2011.
    [2] M. Pelgrom, Analog-to-Digital Conversion. Netherlands: Springer, 2010.
    [3] B. Razavi, Design of Analog Cmos Integrated Circuits. Boston. MA: McGraw-Hill, 2001.
    [4] W. Sansen, Analog Design Essentials. Dordrecht, Netherlands: Springer, 2006.
    [5] D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons, 1997.
    [6] F. Maloberti, Data Converters. Dordrecht, Netherlands: Springer, 2010.
    [7] Y. Geerts, M. Steyaert, and W. Sansen, Design of Multi-Bit Delta-Sigma A/D Converters. Boston. MA: Kluwer, 2002.
    [8] S. R. Norsworthy, R. Schreier, G. C. Temes, I. Circuit, and S. Society, Delta-Sigma Data Converters: Theory, Design, and Simulation. New York: IEEE Press, 1997.
    [9] S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power, Sigma-Delta Modulators. Boston. MA: Kluwer, 1999.
    [10] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters. New York: IEEE Press, 2005.
    [11] L. Yao, M. Steyaert, and W. Sansen, Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS. Dordrecht, German: Springer, 2006.
    [12] J. Silva, U. K. Moon, J. Steensgaard, and G. C. Temes, "Wideband low-distortion delta-sigma ADC topology," Electron. Lett., vol. 37, pp. 737-738, Jun. 2001.
    [13] A. Gharbiya and D. A. Johns, "On the implementation of input-feedforward delta-sigma modulators," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, pp. 453-457, Jun. 2006.
    [14] K. Lee and G. C. Temes, "Improved low-distortion ΔΣ ADC topology," in Proc. IEEE Int. Symp. Circuits and Syst., May 2009, pp. 1341-1344.
    [15] A. A. Hamoui and K. Martin, "High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling delta-sigma ADCs for broad-band applications," IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 51, pp. 72-85, Jan. 2004.
    [16] J. Silva, U. K. Moon, and G. C. Temes, "Low-distortion delta-sigma topologies for MASH architectures," in Proc. IEEE Int. Symp. Circuits and Syst., May 2004, pp. I-1144-7 Vol.1.
    [17] R. Jeongjin, B. Sanho, C. Youngkil, R. Hyungdong, Y. G. Kim, and J. K. Kee, "A 0.9-V 60-μW 1-Bit fourth-order delta-sigma modulator with 83-dB dynamic range," IEEE J. Solid-State Circuits, vol. 43, pp. 361-370, Feb. 2008.
    [18] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato, and A. Baschirotto, "Behavioral modeling of switched-capacitor sigma-delta modulators," IEEE Trans. Circuits Syst. I: Fundam. Theory Appl., vol. 50, pp. 352-364, Mar. 2003.
    [19] G. Suarez, M. Jimenez, and F. O. Fernandez, "Behavioral modeling of switched capacitor integrators with application to ΔΣ modulators," in Proc. IEEE Int. Midwest Symp. Circuits and Syst., Aug. 2006, pp. 709-713.
    [20] H. Zare-Hoseini, I. Kale, and O. Shoaei, "Modeling of switched-capacitor delta-sigma modulators in SIMULINK," IEEE Trans. Instrum. and Meas., vol. 54, pp. 1646-1654, Aug. 2005.
    [21] G. Suarez, M. Jimenez, and F. O. Fernandez, "Behavioral modeling methods for switched-Capacitor ΔΣ modulators," IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 54, pp. 1236-1244, Jun. 2007.
    [22] H. Zare-Hoseini, O. Shoaei, and I. Kale, "Precise behavioural modelling of high-resolution switched-capacitor delta-sigma modulators," in Proc. IEEE Instrum. and Meas. Technol. Conf., May 2004, pp. 1165-1169 Vol.2.
    [23] W. M. Koe and J. Zhang, "Understanding the effect of circuit non-idealities on sigma-delta modulator," in Proc. IEEE Int. Behavioral Modeling and Simulation, Oct. 2002, pp. 94-101.
    [24] P. Arpaia, F. Cennamo, P. Daponte, and H. Schumny, "Modeling and characterization of sigma-delta analog-to-digital converters," in Proc. IEEE Instrum. and Meas. Technol. Conf., May 1998, pp. 96-100 vol.1.
    [25] J. Ruiz-Amaya, J. M. de la Rosa, F. Medeiro, F. V. Fernandez, R. del Rio, B. Perez-Verdu, and A. Rodriguez-Vazquez, "An optimization-based tool for the high-level synthesis of discrete-time and continuous-time sigma-delta modulators in the Matlab/Simulink environment," in Proc. IEEE Int. Symp. Circuits and Syst., May 2004, pp. V-97-V-100 Vol.5.
    [26] J. Ruiz-Amaya, J. M. de la Rosa, F. Medeiro, F. V. Fernandez, R. del Rio, B. Perez-Verdu, and A. Rodriguez-Vazquez, "MATLAB/SIMULINK-based high-level synthesis of discrete-time and continuous-time sigma-delta modulators," in Proc. Eur. Conf. Design Automat. and Test, Feb. 2004, pp. 150-155 Vol.3.
    [27] W. Shen and G. C. Temes, "Double-sampled ΔΣ modulator with relaxed feedback timing," in Proc. IEEE Int. Midwest Symp. Circuits and Syst., Aug. 2009, pp. 393-396.
    [28] Y. Wang, P. K. Hanumolu, and G. C. Temes, "Design techniques for wideband discrete-time delta-sigma ADCs with extra loop delay," IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 58, pp. 1518-1530, Jul. 2011.
    [29] Y. Wang, C. H. Chen, W. Yu, and G. C. Temes, "Noise-coupled low-power incremental ADCs," in Proc. IEEE Int. Symp. Circuits and Syst., May 2010, pp. 4001-4004.
    [30] K. Lee, G. C. Temes, and F. Maloberti, "Noise-coupled multi-Cell delta-sigma ADCs," in Proc. IEEE Int. Symp. Circuits and Syst., May 2007, pp. 249-252.
    [31] R. Zanbaghi, T. S. Fiez, and G. C. Temes, "A new zero-optimization scheme for noise-coupled ΔΣ ADCs," in Proc. IEEE Int. Symp. Circuits and Syst., May 2010, pp. 2163-2166.
    [32] Y. Wang and G. C. Temes, "Noise-coupled continuous-time delta-sigma ADCs," Electron. Lett., vol. 45, pp. 302-303, Mar. 2009.
    [33] K. Lee, J. Chae, M. Aniya, K. Hamashita, K. Takasuka, S. Takeuchi, and G. C. Temes, "A noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, 98 dB THD, and 79 dB SNDR," IEEE J. Solid-State Circuits, vol. 43, pp. 2601-2612, Dec. 2008.
    [34] S. C. Huang and T. Y. Wang, "A tunable SC bandpass delta-sigma modulator with noise-coupled architecture," in Proc. IEEE Int. Midwest Symp. Circuits and Syst., Aug. 2011, pp. 1-4.
    [35] K. H. Lee, K. S. Kim, and S. H. Lee, "A 12b 50 MS/s 21.6 mW 0.18μm CMOS ADC maximally sharing capacitors and op-amps," IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 58, pp. 2127-2136, Sept. 2011.
    [36] D. Kanemoto, T. Ido, and K. Taniguchi, "A 7.5mW 101dB SNR low-power high-performance audio delta-sigma modulator utilizing opamp sharing technique," in Proc. Int. SoC Design Conf., Nov. 2011, pp. 66-69.
    [37] R. Schreier, J. Silva, J. Steensgaard, and G. C. Temes, "Design-oriented estimation of thermal noise in switched-capacitor circuits," IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 52, pp. 2358-2368, Nov. 2005.
    [38] A. Nilchi and D. A. Johns, "Charge-pump based switched-capacitor integrator for ΔΣ modulators," Electron. Lett., vol. 46, pp. 400-401, Mar. 2010.
    [39] A. Nilchi and D. A. Johns, "Analysis of thermal noise and the effect of parasitics in the charge-pump integrator," in Proc. Ph.D. Research in Microelectron. and Electron., Jul. 2010, pp. 1-4.
    [40] W. Shen, T. Wang, and G. C. Temes, "Low distortion ΔΣ modulator employing modified charge-pump based switched-capacitor integrator," in Proc. IEEE Int. Midwest Symp. Circuits and Syst., Aug. 2010, pp. 901-904.
    [41] T. Wang and G. C. Temes, "Low-power switched-capacitor integrator for delta-sigma ADCs," in Proc. IEEE Int. Midwest Symp. Circuits and Syst., Aug. 2010, pp. 493-496.
    [42] J. Steensgaard, "Bootstrapped low-voltage analog switches," in Proc. IEEE Int. Symp. Circuits and Syst., Jul. 1999, pp. 29-32 vol.2.
    [43] L. Wang, J. Ren, W. Yin, T. Chen, and J. Xu, "A high-speed high-resolution low-distortion CMOS bootstrapped switch," in Proc. IEEE Int. Symp. Circuits and Syst., May 2007, pp. 1721-1724.
    [44] M. Dessouky and A. Kaiser, "A 1 V 1 mW digital-audio delta-sigma modulator with 88 dB dynamic range using local switch bootstrapping," in Proc. IEEE Cust. Int. Circuits Conf., May 2000, pp. 13-16.
    [45] D. Aksin, M. A. Al-Shyoukh, and F. Maloberti, "A bootstrapped switch for precise sampling of inputs with signal range beyond supply voltage," in Proc. IEEE Cust. Int. Circuits Conf., Sept. 2005, pp. 743-746.
    [46] T. Wang and G. C. Temes, "Low-power parasitic-insensitive switched-capacitor integrator for delta-sigma ADCs," Electron. Lett., vol. 46, pp. 1114-1116, Aug. 2010.
    [47] M. Yavari and O. Shoaei, "A novel fully-differential class AB folded-cascode OTA for switched-capacitor applications," in Proc. IEEE Int. Conf. Electron. Circuits and Syst., Dec. 2005, pp. 1-4.
    [48] M. Taherzadeh-Sani, R. Lotfi, and O. Shoaei, "Pseudo-class-AB telescopic-cascode operational amplifier," Electron. Lett., vol. 40, pp. 219-221, Feb. 2004.
    [49] O. Choksi and L. R. Carley, "Analysis of switched-capacitor common-mode feedback circuit," IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., vol. 50, pp. 906-917, Dec. 2003.
    [50] O. Rajaee, T. Musah, N. Maghari, S. Takeuchi, M. Aniya, K. Hamashita, and U. K. Moon, "Design of a 79 dB 80 MHz 8X-OSR hybrid delta-sigma/pipelined ADC," IEEE J. Solid-State Circuits, vol. 45, pp. 719-730, Apr. 2010.
    [51] O. Rajaee, S. Takeuchi, M. Aniya, K. Hamashita, and U. K. Moon, "A 1.2V, 78dB HDSP ADC with 3.1V input signal range," in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2010, pp. 1-4.
    [52] J. F. Lin, S. J. Chang, C. F. Chiu, H. H. Tsai, and J. J. Wang, "Low-power and wide-bandwidth cyclic ADC with capacitor and opamp reuse techniques for CMOS image sensor application," IEEE Sensors J., vol. 9, pp. 2044-2054, Dec. 2009.
    [53] T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 30, pp. 166-172, Mar. 1995.
    [54] L. Sumanen, M. Waltari, V. Hakkarainen, and K. Halonen, "CMOS dynamic comparators for pipeline A/D converters," in Proc. IEEE Int. Symp. Circuits and Syst., Aug. 2002, pp. V-157-V-160 vol.5.
    [55] J. R. Yuan, I. Karlsson, and C. Svensson, "A true single-phase-clock dynamic CMOS circuit technique," IEEE J. Solid-State Circuits, vol. 22, pp. 899-901, Oct. 1987.
    [56] J. R. Yuan and C. Svensson, "High-speed CMOS circuit technique," IEEE J. Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989.
    [57] L. Bos, G. Vandersteen, P. Rombouts, A. Geis, A. Morgado, Y. Rolain, G. Van der Plas, and J. Ryckaert, "Multirate cascaded discrete-time low-pass ΔΣ modulator for GSM/Bluetooth/UMTS," IEEE J. Solid-State Circuits, vol. 45, pp. 1198-1208, Jun. 2010.
    [58] N. Waki, H. Sato, A. Hyogo, and K. Sekine, "Input-feedforward two-path band-pass delta-sigma modulator based on horizontal or vertical opamp sharing technique," IEICE Trans. Electron., vol. E91-A, pp. 443-453, Feb. 2008.
    [59] K. Lee, M. R. Miller, and G. C. Temes, "An 8.1 mW, 82 dB delta-sigma ADC with 1.9 MHz BW and 98 dB THD," IEEE J. Solid-State Circuits, vol. 44, pp. 2202-2211, Aug. 2009.
    [60] Y. Nishida and G. C. Temes, "An enhanced dual-path ΔΣ analog-to-digital converter," in Proc. IEEE Int. Symp. Circuits and Syst., May 2009, pp. 1333-1336.
    [61] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1439, Oct. 1989.
    [62] J. B. Shyu, G. C. Temes, and K. Yao, "Random errors in MOS capacitors," IEEE J. Solid-State Circuits, vol. 17, pp. 1070-1076, Dec. 1982.
    [63] B. H. Leung and S. Sutarja, "Multibit sigma-delta A/D converter incorporating a novel class of dynamic element matching techniques," IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., vol. 39, pp. 35-51, Jan. 1992.
    [64] L. R. Carley, "A noise-shaping coder topology for 15+ bit converters," IEEE J. Solid-State Circuits, vol. 24, pp. 267-273, Apr. 1989.
    [65] R. T. Baird and T. S. Fiez, "Improved delta-sigma DAC linearity using data weighted averaging," in Proc. IEEE Int. Symp. Circuits and Syst., May. 1995, pp. 13-16 vol.1.
    [66] R. T. Baird and T. S. Fiez, "Linearity enhancement of multibit delta-sigma A/D and D/A converters using data weighted averaging," IEEE Trans. Circuits Syst. II: Analog Digi. Signal Process., vol. 42, pp. 753-762, Dec. 1995.
    [67] O. Nys and R. K. Henderson, "A 19-bit low-power multibit sigma-delta ADC based on data weighted averaging," IEEE J. Solid-State Circuits, vol. 32, pp. 933-942, Jul. 1997.
    [68] S. M. Yoon, J. B. Park, S. H. Lee, and U. K. Moon, "A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching," IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 51, pp. 269-275, May 2004.
    [69] S. M. Yoo, T. H. Oh, J. W. Moon, S. H. Lee, and U. K. Moon, "A 2.5-V 10-b 120 -MSample/s CMOS pipelined ADC with high SFDR," in Proc. IEEE Cus. Int. Circuits Conf., Aug. 2002, pp. 441-444.
    [70] B. Murmann, "ADC Performance Survey 1997-2012," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html

    下載圖示 校內：2015-08-31公開
    校外：2015-08-31公開
    QR CODE