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研究生: 柯家揚
Ko, Cai-Yang
論文名稱: 具低輸出電流漣波之錯相式串級降壓型轉換器之研製
Design and Implementation of an Interleaved Series Buck Converter with Low Output Current Ripple
指導教授: 梁從主
Liang, Tsorng-Juu
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2010
畢業學年度: 98
語文別: 中文
論文頁數: 76
中文關鍵詞: 降壓型轉換器錯相式控制高降壓比
外文關鍵詞: Buck converter, Interleaved control, High-step-down
相關次數: 點閱:110下載:2
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  • 本論文提出一「具低輸出電流漣波之錯相式串級降壓型轉換器」,此電路以兩降壓型轉換器之串級架構組成,以獲得D平方之高降壓比。利用錯相式控制技術,使電路中兩電感電流漣波相互交錯,以達到降低輸出電流漣波、縮小儲能元件體積之目的。本論文首先簡介各類降壓型轉換器,再針對所提出之轉換器的動作原理及電路特性進行分析及探討,並建構及推導出其開迴路電壓模式之小訊號模型,藉以做為分析其系統穩定度及補償器設計之依據。最後,實作一輸入電壓12V,輸出規格1.5V/50A之低壓大電流雛型電路,以驗證轉換器架構及理論之可行性。

    In this thesis, the design and implementation of an interleaved series buck converter with low output current ripple is presented. The converter is constructed by two series step-down converters to acquire high-step-down conversion ratio. The voltage transfer ratio of the converter is D square. By adopting the interleaved control technique, the output current ripple can be reduced and thus the volume of energy storage elements is reduced. The operating principles and circuit characteristics are discussed in this thesis. Also, the small signal models at CCM with voltage mode control are derived for system stability analysis and compensating network design. Finally, a laboratory prototype circuit with input voltage 12 V and output 1.5 V/50 A is implemented to verify the performance of the proposed converter.

    摘 要 I 誌 謝 III 目 錄 IV 圖 目 錄 VII 表 目 錄 X 第一章 緒論 1 1.1 研究動機與背景 1 1.2 論文架構簡介 3 第二章 低電壓大電流之電源轉換器 4 2.1 降壓型轉換器 4 2.2 具倍流整流之隔離型降壓式轉換器 6 2.2.1 推挽式轉換器 7 2.2.2 半橋式轉換器 8 2.2.3 全橋式轉換器 10 2.3 非隔離型高降壓比轉換器 11 2.3.1 單開關串接高降壓比轉換器 11 2.3.2 雙降壓比兩相式降壓轉換器 12 第三章 具低輸出電流漣波之錯相式串級降壓型轉換器 14 3.1 主電路架構 14 3.2 基本動作原理 15 3.3 電路穩態分析 22 3.4 同步整流技術 25 3.5 效率推導分析 27 3.6 輸出電流漣波分析 34 3.7 直流訊號與小訊號模型推導 36 3.7.1 直流分析 38 3.7.2 小訊號分析 39 第四章 硬體電路製作與實驗結果 46 4.1 實作電路之系統規格 46 4.2 實作電路之系統規格 47 4.2.1 儲能元件參數設計 47 4.2.2 開關與同步整流開關之選用 50 4.2.3 電路IC與驅動電路簡介 53 4.3 小訊號模型之驗證 55 4.3.1 輸出對輸入電壓之轉移函數 55 4.3.2 輸入阻抗之轉移函數 56 4.3.3 輸出阻抗之轉移函數 57 4.3.4 輸出對控制電壓之轉移函數 58 4.4 補償網路之設計 59 4.5 實驗結果 63 第五章 結論與未來研究方向 72 5.1 結論 72 5.2 未來研究方向 73 參考文獻 74

    [1]P. P. Gelsinger, P. Gargini, G. Parker, and A. Yu, “Microprocessor circa 2000,” IEEE Spectrum, pp. 43-47, Oct. 1989
    [2]International Technology Roadmap for Semiconductors (ITRS), System Drivers, 2009. At http://vlsicad.ucsd.edu/EDARoadmapWorkshop/2009_SysDrivers.pdf.
    [3]C. P. Basso, Switch-Mode Supplies SPICE Simulations and Practical Design, First Edition, McGraw-Hill, Inc., 2008.
    [4]N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, Second Edition, John Wiley & Sons, Inc., 1995.
    [5]Y. Panov and M. Jovanovic, “Design considerations for 12-V 1.5-V 50-A voltage regulator modules,” IEEE Trans. Power Electron., vol. 16, pp. 776-783, Nov. 2001.
    [6]H. Wetzel, N. Frohleke, F. Meier, and P. Ide, “Comparison of low voltage topologies for voltage regulator modules,” Proc. IEEE IAS’02, vol. 2, pp. 1323-1329, Dec. 2002.
    [7]Y. Ren, M. Xu, K. Yao, and F. C. Lee, “Two-stage 48V power pod exploration for. 64-bit microprocessor,” Proc. IEEE APEC’03, vol. 1, pp. 426-431 , Feb. 2003.
    [8]P. Alou, J. A. Cobos, R. Prieto, O. Garcia, and J. Uceda, “A two stage voltage regulator module with fast transient response capability,” IEEE PESC’03, vol. 1, pp.138-143, Jun. 2003.
    [9]H. Mao, J. A. Abu-Qahouq, S. Luo, and I. Batarseh, “Zero-voltage-switching (ZVS) two-stage approaches with output current sharing for 48 V input DC-DC converter,” Proc. IEEE APEC’04, vol. 2, pp. 1078-1082, Feb. 2004.
    [10]P. Xu, J. Wei, and F. C. Lee, “The active-clamp couple-buck converter-a novel high efficiency voltage regulator module,” Proc. IEEE APEC’01, pp.252-257, 2001.
    [11]T. Tolle, T. Duerbaum, and R. Elferich, “Switching loss contributions of synchronous rectifiers in VRM applications,” Proc. IEEE PESC’03 vol. 1, pp.144-149, Aug. 2003.
    [12]X. Zhou, P. L. Wong, P. Xu, F. C. Lee, and A. Q. Huang, “Investigation of candidate VRM topologies for future microprocessors,” IEEE Trans. Power Electron., vol. 15, no. 6, pp. 1172-1182, Nov. 2000.
    [13]K. Yao, M. Ye, M. Xu, and F. C. Lee, “Tapped-inductor buck converter for high-step-down DC-DC conversion,” IEEE Trans. Power Electron., vol. 20, no. 4, pp. 775-780, Jul. 2005.
    [14]P. Alou, J. A. Oliver, and J. A. Cobos, “Comparison of current doubler rectifier and center tapped rectifier for low voltage applications,” Proc. IEEE APEC’06, pp.744-750, Mar. 2006.
    [15]C. L. Shen, C. T. Tsai, and Y. E. Wu, “High efficiency current-doubler rectifier with low output current ripple and high step-down voltage ratio,” Proc. IEEE ICSET’08, pp.872-876, Nov. 2008.
    [16]Y. Panov and M. M. Jovanovic, “Design and performance evaluation of low-voltage high-current DC/DC on-board modules,” IEEE Trans. Power Electron., vol. 16, no. 1, pp. 26-33, Jan. 2001.
    [17] B. R. Lin, C. L. Huang, and C. H. Tseng, “Analysis and desin of half-bridge converter with two current doubler rectifiers,” Proc. IEEE ICIEA’06, May 2006.
    [18]W. Chen, P. Xu, and F. C. Lee, “The optimization of asymmetric half bridge converter,” Proc. IEEE APEC’01, vol. 2, pp. 703-707, Mar. 2001.
    [19]B. R. Lin, H. K. Chiang, C. H. Tseng, and K. C. Chen, “Analysis and implementation of an asymmetrical half-bridge converter,” Proc. IEEE PEDS’05, vol. 1, pp. 407-412, Apr. 2005.
    [20]N. H. Kutkut , “A full bridge soft switched telecom power supply with a current doubler rectifier,” Proc. IEEE INTELEC’97, pp.344-351, Oct. 1997.
    [21]A. Pietkiewicz and D. Tollik, “Coupled-inductor current-doubler topology in phase-shifted full-bridge DC-DC converter,” Proc. IEEE INTELEC’98, pp. 41-48, 1998.
    [22]D. Maksimovic and S. Cuk, “Switching converters with wide DC conversion range,” IEEE Trans. Power Electron., vol. 6, no. 1, pp. 151-157, Jan. 1991.
    [23]K. Nishijima, K. Harada, T. Nakano, T. Nabeshima, and T. Sato, “Analysis of double step-down two-phase buck converter for VRM,” Proc. IEEE INTELEC’05, pp. 497-502, Sep. 2005.
    [24]K. Nishijima, K. Harada, T. Nakano, T. Nabeshima, and T. Sato, “A double step-down two-phase buck converter for VRM,” Proc. IEEE PECON’05, pp. 1-8, Apr. 2005.
    [25]R. Tymerski and V. Vorperian, “Generation and classification of PWM dc-to-dc converters,” IEEE Trans. Aerosp. Electron. Syst., vol. 24, pp. 743–754, Nov. 1988.
    [26]Z. J. Shen, Y. Xiong, X. Cheng, Y. Fu, and P. Kumar, “Power MOSFET switching loss analysis: a new insight,” IEEE IAS’06, vol. 3, pp. 1438-1442, Oct. 2006.
    [27]R. D. Middlebrook, “Small-signal modeling of pulse-width modulated switched-mode power converters,” Proc. IEEE, vol. 76, no. 4, pp. 343-354, Apr. 1988.
    [28]V. Vorperian, R. Tymerski, and F. C. Lee, “Equivalent circuit models for resonant and PWM switches,” IEEE Trans. Power Electron., vol. 4, no. 2, pp. 205-214, Apr. 1989.
    [29]T. F. Wu and Y. K. Chen, “Modeling PWM DC/DC converters out of basic converter units,” IEEE Trans. Power Electron., vol. 13, no. 5, pp. 870-881, Sep. 1998.
    [30]V. Verperian, “Simplified analysis of PWM converters using model of PWM switch Part I: Continues conduction mode,” IEEE Trans. Power Electron., vol. 26, no.3, pp.490-496, May 1990.
    [31]L. Jinjun, F. Xiaogang, F. C. Lee, and D. Borojevich, “Stability margin monitoring for DC distributed power systems via perturbation approaches,” IEEE Trans. Power Electron., vol. 18, no. 6, pp.1254–1261, Nov. 2003.
    [32]K. Yao, Y. Meng, P. Xu, and F. C. Lee, “Design considerations for VRM transient response based on the output impedance,” Proc. IEEE APEC’02, vol. 1, pp.14-20, Mar. 2002.
    [33]Y. K. Lo, S. C. Yen, and J. M. Wang, “Linearization of the control-to-output transfer function for a PWM buck-boost converter,” Proc. IEEE ISIE’04, vol. 2, pp. 875-877, May 2004.
    [34]B. E. Mohandes and C. Lee, “Designing low-voltage DC/DC converters with the Si9145,” Vishay Siliconix Corporation, Application Note AN715.
    [35]UC3825 Datasheet, Texas Instrument, 2008.
    [36]UCC37325 Datasheet, Texas Instrument, 2002.
    [37]L. Balogh, “Design and application guide for high speed MOSFET gate drive circuits,” Proc. TI-Unitrode Power Supply Design Sem., pp. 1–37, 2000.
    [38]V. J. Thottuvelil and G. C. Verghese, “Simulation Based Exploration of Aliasing Effects in PWM Power Converters,” IEEE COMPEL Workshop, pp. 177-184, Jul. 1998.
    [39]A. I. Pressman, Switching Power Supply Design, Second Edition, McGraw-Hill, Inc., 1998.
    [40]IRF2804 Datasheet, International Rectifier, 2008.
    [41]J. Klein, “Synchronous buck MOSFET loss calculations with excel model,” Fairchild Semiconductor Corporation, Application Note AN-6005, Jan. 2006.

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