本論文將近年來學術界對極低功耗參考電壓以及降壓型轉換器的研究進行整理，並透過晶片下線的方式實作一個整合了極低功耗參考電壓之降壓型電源轉換晶片。參考電壓的部分採用全MOS架構實現，並且使用電路設計的技巧降低全MOS架構參考電壓有較大製程變異的問題；降壓型轉換器則是以先前本實驗室開發的架構為基礎，加入部分額外電路後使得能夠與本作品之電壓參考電路整合為同一個系統。
本作品使用TSMC 0.18um 1.8V/3.3V 1P6M Mixed Signal製程進行晶片設計。在晶片量測結果上，本作品靜態電流總和為411nA，在大部分的負載範圍均能保持80%以上的轉換效率，參考電壓的PVT變異亦控制在±2.2%的範圍內。

In this thesis, we study and design the ultra-low power voltage reference and buck converter, and propose the power converter IC with ultra-low power voltage reference and ultra-low power buck converter. In this work, the voltage reference circuit is implemented with MOS-only technique, and the reference voltage variation caused by MOS-only structure is suppressed through circuit design technique. The buck converter is based on the pervious study, and integrate the voltage reference circuit of this work into a system by adding the additional circuit.
This work uses TSMC 0.18um 1.8V/3.3V 1P6M Mixed Signal process for chip design. On the chip measurement results, the quiescent current of this work is only 411nA, and the buck converter can meet the efficiency above 80% specification in the most of load range. Also, the reference voltage achieves ±2.2% PVT variation.

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