| 研究生: |
許士杰 Hsu, Shih-Chieh |
|---|---|
| 論文名稱: |
應用於智慧工業之可攜式虛擬處理器系統 Portable Virtual Processor System for Smart Industry |
| 指導教授: |
陳中和
Chen, Chung-Ho |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering |
| 論文出版年: | 2017 |
| 畢業學年度: | 105 |
| 語文別: | 中文 |
| 論文頁數: | 65 |
| 中文關鍵詞: | 數位訊號處理器 、嵌入式系統 、指令集模擬器 、RISC-V 、智慧工業 |
| 外文關鍵詞: | Digital Signal Processor (DSP), Embedded System, Instruction Set Simulator (ISS), RISC-V, Smart Industry |
| 相關次數: | 點閱:104 下載:4 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
自從工業4.0之興起,快速開發新一代產品以滿足上市時間的最終期限是非常重要的。開發商需要評估其需求而選擇匹配之硬件設備,如數位訊號處理器(DSP)、嵌入式系統硬體開發板等。舉例來說,機器手臂被導入自動化生產作業流程時,為了控制機械手臂、監控機械手臂之健康狀況、數據處理、數據接收與傳送,開發商必須選擇一個高性能開發板或者透過通用型電腦來處理多個任務或採用即時作業系統,然而,不論是在何種工業領域中,快速移植應用程式甚至是移植作業系統到不同的硬體平台上是非常不容易的而且需要很多時間去移植。
一個平台上為了支援應用程式可移植性,通常會掛載一個虛擬機器,像是JVM、BlueStacks…等,然而由於工業上使用嵌入式系統開發之硬體平台記憶體資源有限,必須要考慮到其記憶體限制而選擇相對應之虛擬機器。在虛擬機器上應提供軟體除錯功能以利開發者除錯。另一方面,在工業的自動控制領域中,控制器是不可或缺的角色,而市面上所使用的運動控制卡通常以腳本語言進行撰寫並控制工業應用之嵌入式硬體,若是此虛擬機器能提供彈性增加指令的話,而能將每一個指令對應到一個控制演算法,虛擬機器也能如市面上直譯方式將指令轉為相對應之動作,豐富了虛擬機器於工業上之應用。
在本論文中,我們提出了應用於智慧工業之可攜式虛擬處理器系統,虛擬處理器系統是一個C語言撰寫之RISC-V指令集模擬器,而在DSP28335之執行檔大小包含支援GDB的模組僅需23.65 KB而在host x86上僅需43.4 KB,比RISC-V官方提供之指令集模擬器小了約10倍左右。本論文提出之虛擬處理器系統支援GDB遠端除錯功能,除了支援一般TCP/IP溝通方式外,亦提供了使用串行通信 (Serial Communication) 之GDB除錯方式,而考慮到可能會有人透過除錯路徑進行非法記憶體存取,虛擬處理器系統提供了記憶體保護機制來防止這種情況。另一方面,虛擬處理器系統可以擴增指令集來符合工業應用,像是應用於運動控制卡。最後,為了評估虛擬處理器系統,我們選擇DSP28335以及host x86平台作為我們的評估平台,在DSP28335執行效能約0.23 MIPS,而在host x86平台執行效能約40-60 MIPS,並使用了Mibench 作為平台驗證之testbench,另外,我們將FreeRTOS修改並成功運行在本論文提出之虛擬處理器系統上。
This thesis develops a portable, lightweight, secure and GDB-supported virtual processor system for smart industry. The virtual processor system mimics the behavior of a RISC-V processor. RISC-V is an open instruction set architecture and extensible for implementing customized instructions. In this thesis, we implement the customized instructions for calling the native library on the digital signal processor (DSP). The virtual processor system remaps the memory address between the host device and the RISC-V application. When an exception or an interrupt occurs, the virtual processor system will call the trap handler or interrup handler and perform the interrupt sub routine (ISR). The developer can use GDB to debug the RISC-V application through the network or the serial communication interface. To avoid illegal memory access, the virtual processor system also provides the memory protection mechanism.
We evaluate the virtual processor system on the DSP28335 and the host x86 platform with the FreeRTOS as well as the MiBench. The virtual processor system takes 23.65 KB on DSP28335 and 43.4 KB on host x86 platform. The performance on host x86 platform is about 40-60 MIPS and 0.23 MIPS on DSP28335.
[1] Stephen Checkoway , Lucas Davi , Alexandra Dmitrienko , Ahmad-Reza Sadeghi , Hovav Shacham , Marcel Winandy, Return-oriented programming without returns, Proceedings of the 17th ACM conference on Computer and communications security, October 04-08, 2010, Chicago, Illinois, USA [doi>10.1145/1866307.1866370].
[2] }}R. Roemer, E. Buchanan, H. Shacham, and S. Savage. Return-oriented programming: Systems, languages, and applications. Manuscript, 2009. Online: https://cseweb.ucsd.edu/~hovav/papers/rbss09.html.
[3] Sebastian Krahmer. x86-64 Buffer Overflow Exploits and the Borrowed Code Chunks Exploitation Techniques. http://www.suse.de/˜krahmer/no-nx.pdf, September 2005.
[4] Waterman, Andrew, et al. The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0. CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES, 2014.
[5] WATERMAN, A., LEE, Y., AVIZIENIS, R., PATTERSON, D. A., AND ASANOVIC, K. The RISC-V instruction set manual volume II: Privileged architecture version 1.7. Tech. Rep. UCB/EECS-2015-49, EECS Department, University of California, Berkeley, May, 2015.
[6] " RISC-V Foundation | Instruction Set Achitecture (ISA)" , Retrieved June 23, 2017, from https://riscv.org/
[7] M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. MiBench: A Free, Commerically Representative Embedded Benchmark Suite. In Proceedings of the 4th Work. on Workload Characterization, pages 83–94, 2001.
[8] TI Inc., "TMS320F28335 Delfino Microcontroller ", Retrieved June 23, 2017, from http://www.ti.com/product/TMS320F28335.
[9] Ilbeyi, Berkin, Derek Lockhart, and Christopher Batten. "Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator", Extended Abstract for Presentation at the 3rd RISC-V Workshop, January, 2016.
[10] Stallman, Richard M., and Roland H. Pesch. "Debugging with Gdb: The Gnu Source-level Debugger Fifth Edition, for Gdb Version, April 1998". iUniverse Com, 2000.
[11] C.-T. Liu, K.-C. Chen, and C.-H. Chen, “CASL Hypervisor and its Virtualization Platform,” in IEEE International Symp. on Circuit and Systems, ISCAS 2013, pp. 1224-1227, May, 2013.
[12] "FreeRTOS", Retrieved June 23, 2017, from http://www.freertos.org/index.html
[13] "INDUSTRIE 4.0, Smart Manufacturing for the Future", Retrieved June 23, 2017, from https://www.gtai.de/GTAI/Content/EN/Invest/_SharedDocs/Downloads/GTAI/Brochures/Industries/industrie4.0-smart-manufacturing-for-the-future-en.pdf
[14] "Open On-Chip Debugger", Retrieved June 23, 2017, from http://openocd.org/
[15] Chapman, Matthew, Daniel J. Magenheimer, and Parthasarathy Ranganathan. "Magixen: Combining binary translation and virtualization." HP Enterprise Systems and Software Laboratory, pp. 1-15, 2007.
[16] Hu, Shiliang, and James E. Smith, "Using dynamic binary translation to fuse dependent instructions," in proceedings of n-th International Symposium on Code Generation and Optimization (CGO’04), Palo Alto, California, pp.213¸March, 2004.
[17] Gatliff, Bill. "Embedding with GNU: GNU debugger." Embedded Systems Programming, 12: 80-95, 1999
[18] Minheng Tan, "A minimal GDB stub for embedded remote debugging", Retrieved June 23, 2017, http://www1.cs.columbia.edu/~sedwards/c1asses/2002/w4995-02/tan-final.pdf, 2002.
[19] "EECS 700 - Virtual Machines", Retrieved June 23, 2017, from http://www.ittc.ku.edu/~kulkarni/teaching/EECS768/
[20] "The Java® Virtual Machine Specification Java SE 8 Edition", Retrieved June 23, 2017, from https://docs.oracle.com/javase/specs/jvms/se8/html/index.html