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研究生：	陳俊仁 Chen, Jun-Ren
論文名稱：	一以Cyclone 10為基礎之FPGA開發版的印刷電路板佈線研究 A study of PCB layout for FPGA development board based on Cyclone 10
指導教授：	陳進興 Chen, Chin-Hsing
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering
論文出版年：	2021
畢業學年度：	109
語文別：	英文
論文頁數：	56
中文關鍵詞：	現場可程式化邏輯閘陣列 (FPGA) 、嵌入式系統、印刷電路板、微電腦接地
外文關鍵詞：	Field programmable logic gate array (FPGA), embedded system, printed circuit board, microcomputer grounding
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在本篇論文裡，經由組合現存的兩片開發板的周邊元件，我們設計了一具備我們想要功能的一開發板。對於我們使用的設計軟體中所沒有的Symbol及封裝技術，我們則自己製造出所需元件的Symbol與封裝。本論文也探索幾個設計原理藉以消除EMI對高頻訊號的干擾，以確保信號的完整性。
在我們的設計裡，導線均有刻意安排使其能逃脫BGA封裝的IC。我們設計的開發板共有三層訊號層，一層接地層及兩層供電層。我們把FPGA與它的系統控制器IO所用最多的電壓分別建立兩個電源層(3.3V與2.5V)，以使BGA內部的電源輸入可以在BGA焊點與焊點之間透過穿孔連接電源層，這大大降低了佈線的複雜度。FPGA與系統控制器的旁路電容則透過穿孔直接連接，以達到最好的濾波效果。

In this thesis, we design a development board with desired functionalities by assembling the peripherals from two existing embedded development boards. For those devices whose symbols and packaging techniques are not available in the design software, we create them by ourself. We explore several design concepts to eliminate the effects of EMI on high-speed signals to ensure signal integrity so that the success of layout can be achieved.
In the layout process, the conducting wires are carefully arranged to escape from the BGA package. Our designed board consists of six layers, including three signals , one ground plane and two power planes (3.3V and 2.5V) for most voltages used by the FPGA and the system controller IO. In our design, the power input inside the BGA can be connected to the power layer between the BGA solder joints through vias, which greatly reduces the complexity of wiring. The bypass capacitors of the FPGA and the system controller were directly connected through vias to achieve the best filtering effect.

摘要 I
Abstract II
誌謝 III
Acknowledgment IV
Contents V
List of Tables VII
List of Figures VII
Chapter 1 Introduction 1
1.1 Printed Circuit Board 1
1.2 Kicad 1
1.3 Electromagnetic interference (EMI) 4
1.4 Motivation and Contribution 5
1.5 Thesis Outline 6
Chapter 2 Basics of Printed Circuit Board 7
2.1 RF Energy Generation and Crosstalk 7
2.2 Solutions to Reducing Unwanted RF Energy And Crosstalk 11
2.3 PCB Design Techniques 12
2.3.1 Layer Stacking Allocation 12
2.3.2 Image Planes (Power Planes) 13
2.3.3 Routing Topologies and Differential Pair 14
2.3.4 Bypass And Decoupling Capacitors 16
2.3.5 Impedance Matching 19
Chapter 3 Design of the Proposed Development Board 21
3.1 Overview 21
3.2 Architecture of the Proposed Development Board 22
3.3 DC-DC Converter (Power Regulator) 23
3.4 Oscillator 26
3.5 FPGA 28
3.6 HyperRAM 31
3.7 Ethernet 32
3.8 VGA 35
Chapter 4 Implementation of the Proposed System 37
4.1 Schematic of Our System 37
4.2 Layout of Our System 44
Chapter 5 Conclusions and Future Work 54
References 56
                                    

[1] M. I. Montrose, Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers. 2000, pp. 3,4,14,19,20,38,55,56,66,82,83,85,101,104,107,116.
[2] T. Instruments. (1999). PCB Design Guidelines For Reduced EMI.
[3] D. L. Jones. (2004). PCB Design Tutorial.
[4] Intel. (2016). Schematic of Cylcone 10 LP FPGA.
[5] T. T. Inc. (2013). Schematic of DE0-CV Development Board.
[6] Intel. (2020). Intel® MAX® 10 FPGA Device Datasheet.
[7] Intel. (2018). Datasheet of EN5329QI.
[8] Intel. (2018). Datasheet of EP5358HUI
[9] Enpirion. (2012). Datasheet of EN5339QI.
[10] S. Labs. (2020). Datasheet of Si5351.
[11] D. G. Bailey, Design for Embedded Image Processing on FPGAs. 2011, pp. 21-23.
[12] I. S. S. Inc. (2018). Datasheet of IS66WVH16M8ALL/BLL.
[13] A. Wolke, "Tutorial: Digital to Analog Conversion – The R-2R DAC."
[14] YAGEO. (2019). Datasheet of YC124-JR-0710.
[15] Intel. (2019). AN 114: Board Design Guidelines for Intel Programmable Device Packages.
[16] L. Semicondiuctor. (2017). PCB Layout Recommendations for BGA Packages.

2026-08-20公開

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