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研究生： 莊閔欽
Chuang, Min-Chin
論文名稱： 適用於主動式液晶顯示器之新式非晶矽閘極驅動電路設計
New a-Si:H Gate Driver Circuit Design for AM-LCD Application
指導教授： 林志隆
Lin, Chih-Lung
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2010
畢業學年度： 98
語文別： 英文
論文頁數： 52
中文關鍵詞： 非晶矽薄膜電晶體 、閘極驅動電路 、主動式液晶顯示器
外文關鍵詞： hydrogenated amorphous silicon thin-film transistor, gate driver circuit, AM-LCDs
相關次數： 點閱：98  下載：0 
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    • 近年來，為降低面板的成本，主動式液晶顯示器之閘極驅動電路採用薄膜電晶體技術設計已逐漸成為主流的趨勢。然而非晶矽薄膜電晶體元件會因為長時間的使用或者是高偏壓施加而產生臨界電壓的漂移，進而影響到驅動電路的穩定度，並且造成畫面的顯示品質下降。
    本論文即針對上述問題提出三個新式非晶矽閘極驅動電路，且透過電路模擬軟體以及實驗結果驗證其電路之有效性。第一個電路是採用十二顆電晶體、三顆電容和四組訊號源的架構，結合交流式電流驅動方法來減緩電路中電晶體臨界電壓漂移的現象，同時抑制輸出電壓產生浮動的現象。實驗結果顯示在100 ℃下，此電路能穩定操作超過240小時，輸出點充、放電達穩態所需時間分別為2.1 μs和2.1 μs。第二個電路由八顆電晶體、一顆電容和兩組訊號源所組成，擁有架構簡單和輸出低雜訊的優點。此外，藉著降低訊號源之電壓擺幅 (40 V降至25 V)，薄膜電晶體臨界電壓的變異性同時也能被抑制，確保延長電路的有效操作時間。模擬結果顯示，此電路的輸出波形相當穩定，同時雜訊非常的低。此電路輸出點充、放電達穩態所需時間分別為5.8 μs和4.6 μs，亦符合高品質顯示器面板之規格。第三個電路由十顆電晶體、三顆電容和三組訊號源所構成，結合了上述兩電路的優點:第一，交流式電流驅動方法仍被使用來降低電晶體臨界電壓的漂移同時避免輸出產生浮動現象，且架構較為精簡;第二，此電路能夠藉由適當的設計調變施加於薄膜電晶體上的電壓擺幅，降低其臨界電壓的變異性，使電路能更穩定且長時間地操作。模擬結果顯示此電路的輸出不因薄膜電晶體臨界電壓的變異性而受影響，且輸出波形也非常的穩定，不會產生波動的現象，輸出點充、放電達穩態所需時間分別為4.9 μs和 5.1 μs。

    Reducing the cost of active matrix liquid crystal displays (AM-LCDs) by utilizing thin film transistors (TFTs) as the switching component for the gate driver circuit has been a mainstream trend in recent years. However, the threshold voltage shifts of hydrogenated amorphous silicon (a-Si:H) TFTs due to long-term operation or high-bias stress deteriorate the stability of the gate driver circuit, ultimately lowering the image quality of the AM-LCDs.
    This thesis proposes three novel gate driver circuits and verifies their effectiveness by experiments and simulations. The first circuit, composed of 12 TFTs, three capacitors and 4 clock signals, utilizes an AC-driving structure in the proposed circuit to suppress the VTH shift of TFTs and prevent the row line from floating. Experimental results indicate that this circuit can operate stably for more than 240 hours at 100 ℃. The rising time (TRISE) and falling time (TFALL) of the output voltage in the first circuit are 2.1 μs and 2.1 μs, respectively.
    The second circuit, consisting of 8 TFTs, 1 capacitor and 2 clock signals, has a simple structure and low noise interference of output voltages. Additionally, reducing the voltage swings of the clock signals in the circuit can suppress the VTH shift of TFTs and extend the effective operating time. Simulation results demonstrate that the proposed gate driver circuit can generate stable output voltages with low noise interference. Moreover, The TRISE and TFALL of the output voltage in the second circuit are 5.8 μs and 4.6 μs, which still corresponds to the specifications of high-quality image of displays.
    The third circuit, consisting of 10 TFTs, 3 capacitors and 3 clock signals, combines the merits of the above mentioned circuits. First, the AC-driving structure is also used to suppress the VTH shifts of TFTs and prevent the outputs from floating with a simpler structure. Moreover, modulating the voltage swings of clock signals stressed on the pull-down TFT significantly reduces the VTH shift to ensure the long-term operation of the proposed circuit. Simulation results indicate that the proposed circuit has a high immunity against the VTH shift in TFTs and output fluctuations. Furthermore, TRISE and TFALL of the output voltage in the third circuit are 4.9 μs and 5.1 μs, respectively.

    Contents Pages Chinese Abstract ⅰ English Abstract ⅱ Acknowledgements ⅳ Contents ⅴ Table Captions vii Figure Captions viii Chapter 1 Introduction 1.1 Background 1 1.2 Motivation and Previous Researches 4 1.3 Thesis Organization 8 Chapter 2 A Stable a-Si:H TFT Gate Driver Circuit with Reducing Clock Duty Ratio 2.1 Introduction 9 2.2 Circuit Schematic and Operation 10 2.3 Measurement Results and Discussions 11 2.4 Conclusions 13 Chapter 3 An a-Si:H TFT Gate Driver Circuit with Simplified Driving Structure 3.1 Introduction 19 3.2 Circuit Schematic and Operation 20 3.3 Simulation Results and Discussions 22 3.4 Conclusions 25 Chapter 4 Design of Highly Reliable a-Si:H Gate Driver Circuit with High Immunity against the Threshold Voltage Shift of TFT and Output Fluctuations 4.1 Introduction 32 4.2 Circuit Schematic and Operation 34 4.3 Measurement and Simulation Results 35 4.4 Conclusions 39 Chapter 5 Conclusions 46 References 48 Vita 52 Table Captions Pages Table 1.1 Comparisons of source driver ICs and gate driver ICs 3 Table 1.2 Design parameters of the proposed pixel circuit 3 Table 1.3 Comparison of a-Si and LTPS technologies 4 Table 1.4 Comparison of previous researches and proposed circuits 7 Table 2.1 Measurement of the OUT[N] voltage, rising and falling times at 100 ℃ 17 Table 2.2 Design parameters of the proposed gate driver circuit 18 Table 3.1 Design parameters of the proposed gate driver circuit 30 Table 3.2 Comparisons of the two proposed gate driver circuits 31 Table 4.1 Design parameters of the proposed gate driver circuit 44 Table 4.2 Parameters for estimated VTH shifts of TFTs in the proposed circuit 45 Table 4.3 Comparisons of the proposed and modified gate driver circuits 45 Table 5.1 Comparisons of three gate driver circuits 47 Figure Captions Pages Fig. 1.1 Categories of flat panel displays (FPDs) 2 Fig. 1.2 System block diagram of TFT-LCDs 2 Fig. 1.3 Low noise integrated gate driver, proposed by Jang et al. (2005) 5 Fig. 1.4 a-Si:H S-R latch gate driver circuit, proposed by Kim et al. (2006) 5 Fig. 1.5 Gate circuit with TFT VTH compensation capability, proposed by ITRI (2007) 6 Fig. 1.6 Gate circuit with AC-driving structure, proposed by Jang et al. (2008) 6 Fig. 2.1 Block diagram of proposed gate driver circuit 14 Fig. 2.2 Proposed a-Si gate driver circuit:(a) Schematic diagram (b) Timing diagram (c) Optical image 15 Fig. 2.3 Measurement of Input signal, OUT node, and the applied clock signals.. …………………………………………………………………………………………...16 Fig. 2.4 Proposed gate driver circuit under 100℃ stress: (a) measured voltage of OUT[N] node, (b) measured voltage of Q[N] node 17 Fig. 3.1 Block diagram of proposed gate driver circuit 26 Fig. 3.2 Proposed gate driver circuit: (a) Schematic diagram (b) Timing diagram………………………………………………………………………………… 26 Fig. 3.3 Circuit operations of proposed gate driver circuit: (a) Period (1) (b) Period (2) 27 Fig. 3.4 Simulation results for (a) Output voltages of proposed circuit (b) Voltages of Q[n], G[n], and OUT[n] nodes, respectively 28 Fig. 3.5 Simulation results for the rising and falling times of the output voltage. 28 Fig. 3.6 (a) Related rising times (TRISE) by modulating voltage source of VDD1 (b)Related falling times (TFALL) with various widths of T8. 29 Fig. 3.7 Schematic diagram of modified gate driver circuit 29 Fig. 3.8 Simulated rising and falling times for output voltages of two gate drivers….. 30 Fig. 4.1 Proposed gate driver circuit: (a) Schematic diagram (b) Timing diagram... …………………………………………………………………………………………...40 Fig. 4.2 Measurement environment for the stress of fabricated a-Si:H TFTs 40 Fig. 4.3 Measured stress-induced changes in transfer characteristics of TFTs 41 Fig. 4.4 Threshold voltage shift of a-Si:H TFT with time under stress of various voltage swings 41 Fig. 4.5 Simulation results for the voltages of (a) Q[n] node (b) Output nodes (c) G[n] node 42 Fig. 4.6 Simulation results of output voltages in the first proposed and modified gate driver circuits by applying various parameters of VTH shifts in TFTs 43 Fig. 4.7 (a) Modified gate driver circuit (b) Simulation results for node voltages of modified circuit 44

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