本論文將近年來學術界對數位式低壓降穩壓器之研究進行整理。首先，了解數位式低壓降穩壓器的應用範圍及基本動作原理。第二，利用系統模型建立一套穩定度設計流程，確保系統的穩定性。第三，整理相關晶片系統應用之研究議題，並探討問題原因。最後，整理近年來關於晶片系統應用的研究文獻，探討目前研究文獻的發展趨勢。
另外，針對晶片系統(SoC)應用，本論文提出具動態電流源陣列之數位雙迴路低壓降穩壓器，其架構能有效地抑制因負載暫態響應所造成的壓差(Over/Undershoot)，並能大幅減少on-chip電容的使用。並且本論文將傳統的數位控制器加以改良，透過加入set/reset控制機制來加速暫態發生後，輸出電壓的回復時間。
本作品使用TSMC 0.18um 1.8V/3.3V 1P6M Mixed Signal製程進行實現。輸入電壓為1.8V、輸出電壓1.2V、最大負載電流30mA、輸出端on-chip電容50pF，在負載電流抽載範圍0.6m-30mA的情況下，Post-sim模擬結果:輸出電壓回穩時間小於150ns，暫態電壓overshoot/undershoot大小分別為18mV/300mV。

In this thesis, we study and design the digital low dropout regulater (DLDO) for system on chip application, and the DLDO is compared with analog low dropout regulater (ALDO). In addition, We discuss the effects of system stability and transient performance by the DLDO system parameters, then propose a system stability design flow by MATLAB SISOtool. It can help the designer to choose system parameters of DLDO to meet the system stability and transient performance.
Finally, we survey the papers of capacitor-less DLDO about fast transient technique and discuss the advantage. And we accomplished a dual-loop capacitor-less DLDO using dynamic current source array and set/reset control bidirectional shift register. The output capacitor less than 50pF and improve transient performance are our target. The proposed dynamic current source array technique can achieve the design target without any passive components. The chip was manufactured by TSMC 0.18-μm 1P6M. The load current range from 0.6mA to 30mA. In transient response, the dynamic current source array technique can reduce over-shoot from 500mV to 180mV and under-shoot from 600mV to 200mV. Besides, the set/reset control bidirectional shift register technique can improve setting time from 1.1μs to 200ns.

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