本論文提出一個具有寬頻域抑制電源漣波雜訊之低壓降線性穩壓器，並有系統地建立了低壓降線性穩壓器和帶差參考電壓兩種電路的設計流程。本論文設計採用了電源漣波減法級和高通濾波器兩種技術，以及一個具有較大頻寬的誤差放大器來達到寬頻域高電源拒斥比的效能。本電路使用TSMC 0.35um CMOS 2-poly 4-metal 標準製程技術。在負載電流為1mA、輸入電壓3.3V條件下量測的 PSR 效能的結果為：10KHz時為-79dB、100KHz的電源拒斥為-82dB、1MHz的電源拒斥為-60dB，在10MHz 為-30dB值。所以本論文提出的低壓降線性穩壓器架構適用於置於DC-DC 轉換器後端來減少輸出漣波。總晶片面積為776×600μm2。

An improved low dropout regulator (LDO) with high power supply rejection (PSR) over wideb frequency range is presented in this thesis, and a systematic design procedure including LDO and bandgap circuits is introduced. The proposed design employs the supply ripple subtraction, high-pass filtering and a wideband error amplifier to achieve high PSR performance over wide frequency range. The proposed LDO implemented with a standard 0.35μm CMOS 2-poly 4-metal process technology. The measured results at load current of 1mA and input voltage of 3.3v show that the PSR of 10k, 100k, 1M and 10M Hz are -79dB, -82dB, -60dB and -30dB respectively. Therefore, it’s well suited for the LDO used as post regulators of DC-DC converters to reduce the output voltage ripples. The active area of this LDO is 776×600μm2.

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