簡易檢索 / 詳目顯示

回結果列表
研究生： 賴俊福
Lai, Chun-Fu
論文名稱： 指令解碼產生器
An Instruction Lexer Generator
指導教授： 陳中和
Chen, Chung-Ho
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2004
畢業學年度： 92
語文別： 英文
論文頁數： 72
中文關鍵詞： 二進位轉換 、解碼器 、自動化輔助設計
外文關鍵詞： Design Automation, Decoder, Binary Translation
相關次數： 點閱：225  下載：2 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 這篇論文介紹了一個新的解碼方案，這是藉由使用一個指令解碼產生器來完成。一般情況下，我們常常藉由使用if-else跟switch case敘述來設計解碼器，但是這並不是一個最佳化且有效率的方式，而且隨著複雜度的提升，會不容易被維護。
    解碼的效能測試針對不同的撰寫風格進行，可以得知的是，藉由直接參考表格的方法比一般的方法更為快速，甚至比switch case的方法更快上46倍之多。這也是所提出的設計所採用的核心技術。
    另一個主題是提供一個設計自動化的方案，為了達到目的，已實作了一個驗證程式來驗證一個已經產生的掃描器，所有核心的函式也都被實作成為函式庫，藉由這樣的方式，設計者可以很容易地實作出自訂的掃描器，甚至是一個發展環境。

    This thesis introduces a new decoder methodology by using an instruction lexer generator. Generally, we often design a decoder using if-else or switch case statements. But this is not an optimized or effective method. Also, it may not be maintained easily due to a growing complexity.
    A decoding benchmark has been done with different coding styles. It seems that referencing tables directly is much faster than general styles, even up to 46 times than switch case control structure. This is the core technique of the proposed design.
    Another motif is to provide a design automation methodology. In order to do this, a verification program is implemented to verify a generated scanner. All core routines are also implemented as a library. By this way, a designer can easily implement a customized scanner, even a development environment.

    Chapter 1 Introduction 1.1–1 1.1 Motivation 1.1–1 1.2 Design Methodology 1.2–2 1.3 Contributions 1.3–2 Chapter 2 Background 1.3–3 2.1 Simulation Methodology 2.1–3 2.1.1 Interpretive Decoding 2.1–3 2.1.2 Compiled Decoding 2.1–3 2.2 Design Automation Tools 2.2–5 2.2.1 Lexical Analyzer 2.2–5 2.2.2 Retargetable Compilation 2.2–5 2.2.3 Retargetable Simulation 2.2–6 2.2.4 Instruction Encoding 2.2–7 Chapter 3 Instruction Set Encoding 2.2–8 3.1 Introduction to Instruction Set Encoding 3.1–8 3.2 Some Instruction Encodings 3.2–9 3.2.1 Sun SPARC V8 3.2–9 3.2.2 ARM V5 3.2–10 3.2.3 MIPS 3.2–11 3.2.4 Intel IA-32 3.2–12 3.3 Issues on Defining an Instruction Encoding 3.3–13 3.3.1 Fixed Length 3.3–13 3.3.2 Variable Length 3.3–14 Chapter 4 Instruction Lexer 3.3–16 4.1 Idea of the Instruction Lexer 4.1–16 4.2 Generation Flow 4.2–17 4.3 Mask Generation Stage 4.3–18 4.3.1 Binary Text Format 4.3–18 4.3.2 Definition File 4.3–20 4.4 Mapping Generation Stage 4.4–21 4.4.1 Byte-Matching Table 4.4–21 4.4.2 Compressed Byte-Matching Table 4.4–22 4.4.3 Class-Matching Table 4.4–22 4.4.4 Scan Table 4.4–23 4.5 Scanner Generation Stage 4.5–26 Chapter 5 Verification and Simulation 4.5–28 5.1 Verification 5.1–28 5.1.1 Table Generation 5.1–28 5.1.2 Test Pattern Generation 5.1–29 5.1.3 Scanner Verification 5.1–29 5.2 Simulation Environment 5.2–30 5.2.1 Configurations 5.2–30 5.2.2 Constraints 5.2–31 5.3 Test-bench 1 5.3–31 5.4 Test-bench 2 5.4–33 5.5 Real Case: ARMv5 5.5–40 Future Work 41 Scanner Description Language 41 NAT (Network Address Translation) Filter Engine 41 Conclusion 42 Reference 43 Appendix A: ARMv5 Definition File 45 Appendix B: Proposal Paper 52

    1. Mehrdad, Prabhat Mishra and Nikil Dutt, “Instruction Set Compiled Simulation : A Technique for Fast and Flexible Instruction Set Simulation,” in Design Automation Conference, pp. 758-763, June 2-6 2003.
    2. Jianwen Zhu and Daniel D. Gajski, “A Retargetable, Ultra-fast Instruction Set Simulator,” in Proceedings of Design Automation and Test Conference in Europe, pp. 9-12, March 1999.
    3. Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr and Andreas Hoffmann, “A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation,” in Design Automation Conference, pp. 22-27, June 10-14 2003.
    4. Maghsoud Abbaspour and Jianwen Zhu, “Retargetable Binary Utilities,” in Design Automation Conference, pp. 331-336, June 10-14 2002.
    5. Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch and Heinrich Meyr, “Instruction Encoding Synthesis for Architecture Exploration using Hierarchical Processor Models,” in Design Automation Conference, Anaheim, California, USA, June 2-6 2003.
    6. Wai Sum Mong, Jianwen Zhu, “A Retargetable Micro-architecture Simulator,” in Design Automation Conference, Anaheim, California, USA, June 2-6 2003.
    7. Austin, T.; Larson, E.; Ernst, D.; “SimpleScalar: An Infrastructure for Computer System Modeling,” IEEE Computer, Volume:35, Issue:2, pp. 59-67, Feb. 2002.
    8. Lex
    http://cholm.home.cern.ch/cholm/misc/ylmm
    9. Flex
    http://www.gnu.org/software/flex
    10. SPARC V8
    http://docs.sun.com/db/doc/806-3774?q=v8+instruction-set
    11. ARM Developer Guide
    http://arm.convergencepromotions.com/catalog/395.htm
    12. LISA Simulator
    http://www.ert.rwth-aachen.de/Projekte/Tools/LISA/
    13. Sulima ISA Simulator
    http://www.cse.unsw.edu.au/~cs9242/sulima/
    14. SimOS
    http://simos.stanford.edu/
    15. Embedded Systems Methodology Group
    http://www.cecs.uci.edu/~cad/
    16. Center for Intelligent Systems Research
    http://www.cisr.gwu.edu/
    17. Virtutech Simics Full-System Simulator
    http://www.simics.com/
    18. Yet Another Machine Simulator
    http://www.niksula.cs.hut.fi/~buenos/

    下載圖示 校內：立即公開
    校外：2004-09-08公開
    QR CODE