本篇論文主要研究視訊解碼器移植到嵌入式系平台後，處理器對外部記憶體存取次數達到最少的軟體優化技術。我們以H.264/AVC和VC-1等視訊解碼器和內嵌有ARM處理器的嵌入式系統平台為例，來探討此嵌入式軟體的優化技術。
將視訊解碼器移植到嵌入式系統平台後，視訊解碼的效能不佳。在視訊解碼器軟體運算過程中，太多的外部記憶體存取動作是主要的問題點。為了解決這個問題，我們提出數種軟體優化技術來優化H.264/AVC及VC-1視訊解碼器的視訊解碼流程。而且，我們也運用了基因演算法的搜尋法則來搜尋出H.264/AVC De-blocking Filter中的近似最佳運算流程順序，此種近似最佳運算流程更能使外部記憶體的存取次數達到最低。我們所提出的軟體優化技術技巧不僅能充分運用處理器內的暫存器做複雜的數值運算，更能減少處理器對外部記憶體的存取次數。
根據軟體模擬結果，以及移植到嵌入式系統開發板後的結果顯示，我們所提出的記憶體存取最佳化技術能夠明顯的改善嵌入式系統上之視訊解碼器的效能。

In this thesis, we focus on the software optimization techniques in reducing the memory accesses after video decoders are implemented on embedded system platforms. We take H.264/AVC, VC-1 video decoders and the embedded system platforms with ARM processors for example to illustrate the software optimization techniques. The video decoding performance is not as good as expected after the video decoders are implemented on embedded system platforms. Too much memory access is the major problem. To solve this kind of problem, we propose several software optimization techniques to optimize the decoding flow of H.264/AVC and VC-1 video decoders. Moreover, we use genetic algorithms to search for the near optimal filtering order of H.264/AVC de-blocking filter. This kind of near optimal filtering order can reduce the external memory access in the de-blocking filter. The proposed optimization techniques above not only can fully utilize the registers to do the complicated computations, but also can reduce the memory access in the decoding flow of video decoders. Simulation results and implementation results on embedded system platform show that our proposed software optimization techniques can really improve the decoding performance of video decoders on embedded system platforms.

[1] T. Van Achteren, G. Deconinck, F. Catthoor, and R. Lauwereins “Data Reuse Exploration Techniques for Loop-dominated Applications” in Proc. of the 2002 Design, Automation and Test in Europe Conference and Exhibition
[2] T. Van Achteren, R. Lauwereins, and F. Catthoor. “Systematic data reuse exploration methodology for irregular access patterns”. In Proc. of IEEE/ACM 13th International Symposium on System Synthesis (ISSS), pages 115-121, Madrid, Spain, Sept 2000.
[3] S.Wuytack, J. Diguet, F. Catthhoor, and H.De Man “Formalized Methodology for Data Reuse Exploration for Low-Power Hierarchical Memory Mappings.” IEEE Trans. on VLSI Systems, 6(4):529-537, Dec.1998
[4] T. Wiegand, G.J. Sulivan, G. Bjntegaard, A. Luthra, “Overview of the H.264/AVC video coding standard,” IEEE Trans. Circuits Syst. Video Technol., vol. 13, Issue 7, pp.560–576, July 2003.
[5] Iain E. G Richardson, H.264 and MPEG-4 video compression: Video Coding for Next-generation Multimedia, Aberdeen, UK, John Wiley, 2003.
[6] Proposed SMPTE Standard for Television: “VC-1 Compressed Video Bitstream Format and Decoding Process,” 2005-08-23
[7] M. Kandemir, “A Compiler-Based Approach for Improving Intra-Iteration Data Reuse” in Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 984-990, Paris
[8] Heiko Falk, Cedric Ghez, Miguel Miranda and Rainer Leupers, “High-level control flow transformations for performance improvement of address-dominated multimedia applications,” in Proc. 11th Workshop on Synthesis and Syst. Integration of Mixed Information Technologies (SASIMI 2003), Hiroshima / Japan, April 2003.
[9] Heiko Falk, “Control flow optimization by loop nest splitting at the source code level,” in Proc. of the Design, Automation and Test in Europe Conference and Exhibition (DATE’03), Munich, Germany, March 2003.
[10] Heiko Falk, “Control flow driven code hoisting at the source code level,” in Proc. 3rd Workshop on Optimizations for DSP and Embedded Systems (ODES) In conjunction with The International Symposium on Code Generation and Optimization (CGO), San Jose, United States, March 2005.
[11] Heiko Falk, Jens Wagner, Andre Schaefer, “Use of a bit-true data flow analysis for processor-specific source code optimization,” in Proc. 4th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), Seoul, Korea, October 2006.
[12] D. E. Goldberg, Genetic Algorithms in Search, Optimization, and machine learning, Reading, MA: Addison-Wesley, 2001.
[13] R. L. Haupt and S. E. Haupt, Practical Genetic Algorithms, New York: Wiley, 2004, pp. 51-93.
[14] C.L Valenzuela, and P.Y. Wang, “VLSI placement and area optimization using a genetic algorithm tobreed normalized postfix expressions” IEEE Trans. Evolutionary Computation, Vol. 6, pp.390-401, Aug 2002
[15] H.Oh, and S. Ha, “Fractional Rate Dataflow Model for Efficient Code Synthesis” J. VLSI Signal Processing, Vol. 37, pp.41-51, May 2004
[16] H.Oh, and S. Ha, “Fractional Rate Dataflow Model and Efficient Code Synthesis for Multimedia Applications” ACM SIGPLAN Notice Vol. 37, pp.12-17, June 2002
[17] S.-H. Wang, W.-H. Peng, Y. He, G.-Y. Lin, C.-Y. Lin, S.-C. Chang, C.N. Wang, and T. Chiang, “A platform based MPEG-4 advanced video coding decoder with block level pipelining,” in Proc. Int. Conf. Multimedia (ICICS-PCM 2003), Singapore, Nov. 2003.
[18] Moshe Y. and Peleg N., ”Implementations of H.264/AVC baseline decoder on different digital signal processors,” in Proc. 47th Int. Symp. Multimedia Sys. Applica. (ELMAR 2005), Zadar, Croatia, June 2005, pp. 37-40.
[19] Y.S Tung, S.W Wang, C.W Tsai, Y.T Yang, and J.L Wu, “DSP-Based Multi-Format Video Decoding Engine for Media Adapter Applications”, IEEE Trans. on Consumer Electronics, Volume 51, Issue 1. pp. 273-280, Feb. 2005.
[20] J. Lee, S.K Moom, W.Y Sung, “H.264 Decoder optimization Exploiting SIMD Instructions” in Asia-Pacific Conf. on Circuits and Systems, Dec. 2004.
[21] G.A. Jian, and J.I Guo, “Low Complexity Multi-Standard Video Player For Portable Multimedia Applications” in IEEE International Conference on Multimedia and Expo, pp. 7-7, July 2007.