| 研究生: |
陳麗天 Chen, Li-Tian |
|---|---|
| 論文名稱: |
應用於 GPU 內部之快取記憶體與主記憶體間之資料傳輸壓縮架構設計 A cache-memory link compression architecture for GPU |
| 指導教授: |
郭致宏
Kuo, Chih-Hung |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2015 |
| 畢業學年度: | 104 |
| 語文別: | 中文 |
| 論文頁數: | 88 |
| 中文關鍵詞: | 記憶體壓縮 、快取壓縮 、資料壓縮 |
| 外文關鍵詞: | Memory Compression, Cache Compression, Data Compression |
| 相關次數: | 點閱:107 下載:0 |
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在本論文中,我們提出一套針對圖形處理器 (Graphics Processing Unit) 之記憶體壓縮架構。 在傳輸大量資料時,利用所提出的壓縮技術節省匯流排頻寬與記憶體空間。 壓縮與解壓縮單元 (Compression and Decompression Unit) 加入在系統的記憶體階層中之快取記憶體與主記憶體間,使資料經過壓縮後降低資料量,達成降低匯流排負擔與主記憶體空間使用的目的。 本論文提出的壓縮演算法為一針對浮點數表示法開發的演算法,並針對 GPU 同時支援浮點數與整數運算的特性,將壓縮架構拓展為可以一次壓縮多個字元,並進一步觀察即利用資料的特性,藉此達到最有效率的壓縮。 經過實驗,我們提出的單字元與四字元壓縮架構在我們的測試環境下,可以提供平均 51.72% 與 46.81% 的壓縮率。 同時我們的壓縮架構估計可以將記憶體存取的能耗降低到 58.77% ,有效降低記憶體存取的功耗。
In this paper, we present a memory-compression architecture for GPU (Graphic Processing Unit). This architecture saves bus bandwidth and memory space for huge data transfer. Our system improves the compression performance by reducing the redundancies in floating-point data. We propose both Single-word and Quad-word memory compression architectures. Comparing with previous works, we get a good improvement, 16.94% of compression ratio on average, 4.3% of area, 9.3% of power and 14% of operation frequency.
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校內:2017-11-24公開